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Fix logic error with silk overlap test.

This commit is contained in:
Jeff Young 2022-06-04 19:33:38 +01:00
parent ecbf5c1e14
commit d14fd5a9da
1 changed files with 6 additions and 3 deletions
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9
pcbnew/drc/drc_test_provider_silk_clearance.cpp
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@ -207,9 +207,12 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run()
// single footprint or on the board.
if( aRefItem->Type() == PCB_SHAPE_T && aTestItem->Type() == PCB_SHAPE_T )
{
// also true when both are nullptr
if( aRefItem->GetParentFootprint() == aTestItem->GetParentFootprint() )
return true;
return true;
}
else if( aRefItem->Type() == PCB_FP_SHAPE_T && aTestItem->Type() == PCB_FP_SHAPE_T
&& aRefItem->GetParentFootprint() == aTestItem->GetParentFootprint() )
{
return true;
}
if( aRefShape->Collide( aTestShape, minClearance, &actual, &pos ) )