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Remove confusion between pad->IsOnLayer and pad->IsPadOnLayer

This commit is contained in:
Jeff Young 2020-09-29 21:40:17 +01:00
parent 31549cdc10
commit d3f8f2b81e
12 changed files with 36 additions and 35 deletions
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6
3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp
View File

@ -488,7 +488,7 @@ void BOARD_ADAPTER::AddPadsShapesWithClearanceToContainer( const MODULE* aModule
continue;
// Skip pad annulus when not connected on this layer (if removing is enabled)
if( !pad->IsPadOnLayer( aLayerId ) && IsCopperLayer( aLayerId ) )
if( !pad->FlashLayer( aLayerId ) && IsCopperLayer( aLayerId ) )
continue;
// NPTH pads are not drawn on layers if the
@ -516,8 +516,8 @@ void BOARD_ADAPTER::AddPadsShapesWithClearanceToContainer( const MODULE* aModule
}
}
const bool isPlated = ( ( aLayerId == F_Cu ) && pad->IsPadOnLayer( F_Mask ) ) ||
( ( aLayerId == B_Cu ) && pad->IsPadOnLayer( B_Mask ) );
const bool isPlated = ( ( aLayerId == F_Cu ) && pad->FlashLayer( F_Mask ) ) ||
( ( aLayerId == B_Cu ) && pad->FlashLayer( B_Mask ) );
if( aSkipPlatedPads && isPlated )
continue;

4
3d-viewer/3d_canvas/create_layer_items.cpp
View File

@ -244,7 +244,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
if( via && !via->IsPadOnLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;
// Add object item to layer container
@ -449,7 +449,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
if( via && !via->IsPadOnLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;
// Add the track/via contour

6
pcbnew/board_items_to_polygon_shape_transform.cpp
View File

@ -126,7 +126,7 @@ void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer,
if( aLayer != UNDEFINED_LAYER && !pad->IsOnLayer(aLayer) )
continue;
if( !pad->IsPadOnLayer( aLayer ) && IsCopperLayer( aLayer ) )
if( !pad->FlashLayer( aLayer ) && IsCopperLayer( aLayer ) )
continue;
// NPTH pads are not drawn on layers if the shape size and pos is the same
@ -153,8 +153,8 @@ void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer,
}
}
const bool isPlated = ( ( aLayer == F_Cu ) && pad->IsPadOnLayer( F_Mask ) ) ||
( ( aLayer == B_Cu ) && pad->IsPadOnLayer( B_Mask ) );
const bool isPlated = ( ( aLayer == F_Cu ) && pad->FlashLayer( F_Mask ) ) ||
( ( aLayer == B_Cu ) && pad->FlashLayer( B_Mask ) );
if( aSkipPlatedPads && isPlated )
continue;

8
pcbnew/class_pad.cpp
View File

@ -181,11 +181,11 @@ bool D_PAD::IsFlipped() const
}
bool D_PAD::IsPadOnLayer( LSET aLayers ) const
bool D_PAD::FlashLayer( LSET aLayers ) const
{
for( auto layer : aLayers.Seq() )
{
if( IsPadOnLayer( layer ) )
if( FlashLayer( layer ) )
return true;
}
@ -193,7 +193,7 @@ bool D_PAD::IsPadOnLayer( LSET aLayers ) const
}
bool D_PAD::IsPadOnLayer( int aLayer ) const
bool D_PAD::FlashLayer( int aLayer ) const
{
BOARD* board = GetBoard();
@ -1194,7 +1194,7 @@ double D_PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
return HIDE;
// Only draw the pad if at least one of the layers it crosses is being displayed
if( board && !IsPadOnLayer( board->GetVisibleLayers() ) )
if( board && !FlashLayer( board->GetVisibleLayers()) )
return HIDE;
// Netnames will be shown only if zoom is appropriate

4
pcbnew/class_pad.h
View File

@ -537,8 +537,8 @@ public:
return m_layerMask[aLayer];
}
bool IsPadOnLayer( int aLayer ) const;
bool IsPadOnLayer( LSET aLayers ) const;
bool FlashLayer( int aLayer ) const;
bool FlashLayer( LSET aLayers ) const;
bool HitTest( const wxPoint& aPosition, int aAccuracy = 0 ) const override;
bool HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy = 0 ) const override;

8
pcbnew/class_track.cpp
View File

@ -137,7 +137,7 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
{
if( !IsPadOnLayer( aLayer ) )
if( !FlashLayer( aLayer ) )
{
if( aSource )
*aSource = _( "removed annular ring" );
@ -466,11 +466,11 @@ void VIA::SanitizeLayers()
}
bool VIA::IsPadOnLayer( LSET aLayers ) const
bool VIA::FlashLayer( LSET aLayers ) const
{
for( auto layer : aLayers.Seq() )
{
if( IsPadOnLayer( layer ) )
if( FlashLayer( layer ) )
return true;
}
@ -478,7 +478,7 @@ bool VIA::IsPadOnLayer( LSET aLayers ) const
}
bool VIA::IsPadOnLayer( int aLayer ) const
bool VIA::FlashLayer( int aLayer ) const
{
BOARD* board = GetBoard();

4
pcbnew/class_track.h
View File

@ -466,14 +466,14 @@ public:
* @param aLayer Layer to check for connectivity
* @return true if connected by pad or track
*/
bool IsPadOnLayer( int aLayer ) const;
bool FlashLayer( int aLayer ) const;
/**
* Checks to see if the via is present on any of the layers in the set
* @param aLayers set of layers to check the via against
* @return true if connected by pad or track on any of the associated layers
*/
bool IsPadOnLayer( LSET aLayers ) const;
bool FlashLayer( LSET aLayers ) const;
/**
* Function SetDrill

10
pcbnew/drc/drc_test_provider_copper_clearance.cpp
View File

@ -275,7 +275,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testCopperDrawItem( BOARD_ITEM* aItem )
SHAPE_SEGMENT padCylinder;
const SHAPE* padShape;
if( pad->IsPadOnLayer( layer ) )
if( pad->FlashLayer( layer ) )
{
padShape = pad->GetEffectiveShape().get();
}
@ -377,7 +377,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I
SHAPE_SEGMENT padCylinder;
const SHAPE* padShape;
if( pad->IsPadOnLayer( aLayer ) )
if( pad->FlashLayer( aLayer ) )
{
padShape = pad->GetEffectiveShape().get();
}
@ -465,7 +465,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I
{
VIA* via = static_cast<VIA*>( track );
if( !via->IsPadOnLayer( aLayer ) )
if( !via->FlashLayer( aLayer ) )
trackSeg.SetWidth( via->GetDrillValue() );
}
@ -684,7 +684,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx,
SHAPE_SEGMENT refPadCylinder;
const SHAPE* refPadShape;
if( refPad->IsPadOnLayer( layer ) )
if( refPad->FlashLayer( layer ) )
{
refPadShape = refPad->GetEffectiveShape().get();
}
@ -704,7 +704,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx,
SHAPE_SEGMENT padCylinder;
const SHAPE* padShape;
if( pad->IsPadOnLayer( layer ) )
if( pad->FlashLayer( layer ) )
{
padShape = pad->GetEffectiveShape().get();
}

2
pcbnew/pcb_painter.cpp
View File

@ -640,7 +640,7 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
/// Vias not connected to copper are optionally not drawn
/// We draw instead the hole size to ensure we show the proper clearance
if( IsCopperLayer( aLayer ) && !aVia->IsPadOnLayer( aLayer ) )
if( IsCopperLayer( aLayer ) && !aVia->FlashLayer( aLayer ) )
radius = getDrillSize(aVia) / 2.0 ;
bool sketchMode = false;

11
pcbnew/plot_board_layers.cpp
View File

@ -200,11 +200,12 @@ void PlotOneBoardLayer( BOARD *aBoard, PLOTTER* aPlotter, PCB_LAYER_ID aLayer,
}
/* Plot a copper layer or mask.
/*
* Plot a copper layer or mask.
* Silk screen layers are not plotted here.
*/
void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
LSET aLayerMask, const PCB_PLOT_PARAMS& aPlotOpt )
void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
const PCB_PLOT_PARAMS& aPlotOpt )
{
BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
@ -249,7 +250,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
}
/// pads not connected to copper are optionally not drawn
if( onCopperLayer && !pad->IsPadOnLayer( aLayerMask ) )
if( onCopperLayer && !pad->FlashLayer( aLayerMask ) )
continue;
COLOR4D color = COLOR4D::BLACK;
@ -422,7 +423,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
int diameter = Via->GetWidth() + 2 * via_margin + width_adj;
/// Vias not connected to copper are optionally not drawn
if( onCopperLayer && !Via->IsPadOnLayer( aLayerMask ) )
if( onCopperLayer && !Via->FlashLayer( aLayerMask ) )
continue;
// Don't draw a null size item :

4
pcbnew/router/pns_kicad_iface.cpp
View File

@ -911,14 +911,14 @@ bool PNS_KICAD_IFACE::IsOnLayer( const PNS::ITEM* aItem, int aLayer )
{
const VIA* via = static_cast<const VIA*>( aItem->Parent() );
return via->IsPadOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
return via->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ));
}
case PCB_PAD_T:
{
const D_PAD* pad = static_cast<const D_PAD*>( aItem->Parent() );
return pad->IsPadOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
return pad->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ));
}
default:

4
pcbnew/zone_filler.cpp
View File

@ -723,7 +723,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
{
for( D_PAD* pad : module->Pads() )
{
if( !pad->IsPadOnLayer( aLayer ) )
if( !pad->FlashLayer( aLayer ) )
{
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
@ -770,7 +770,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
{
VIA* via = static_cast<VIA*>( track );
if( !via->IsPadOnLayer( aLayer ) )
if( !via->FlashLayer( aLayer ) )
{
int radius = via->GetDrillValue() / 2 + bds.GetHolePlatingThickness() + gap;
TransformCircleToPolygon( aHoles, via->GetPosition(), radius, m_maxError );