Remove confusion between pad->IsOnLayer and pad->IsPadOnLayer
This commit is contained in:
parent
31549cdc10
commit
d3f8f2b81e
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@ -488,7 +488,7 @@ void BOARD_ADAPTER::AddPadsShapesWithClearanceToContainer( const MODULE* aModule
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continue;
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continue;
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// Skip pad annulus when not connected on this layer (if removing is enabled)
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// Skip pad annulus when not connected on this layer (if removing is enabled)
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if( !pad->IsPadOnLayer( aLayerId ) && IsCopperLayer( aLayerId ) )
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if( !pad->FlashLayer( aLayerId ) && IsCopperLayer( aLayerId ) )
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continue;
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continue;
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// NPTH pads are not drawn on layers if the
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// NPTH pads are not drawn on layers if the
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@ -516,8 +516,8 @@ void BOARD_ADAPTER::AddPadsShapesWithClearanceToContainer( const MODULE* aModule
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}
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}
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}
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}
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const bool isPlated = ( ( aLayerId == F_Cu ) && pad->IsPadOnLayer( F_Mask ) ) ||
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const bool isPlated = ( ( aLayerId == F_Cu ) && pad->FlashLayer( F_Mask ) ) ||
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( ( aLayerId == B_Cu ) && pad->IsPadOnLayer( B_Mask ) );
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( ( aLayerId == B_Cu ) && pad->FlashLayer( B_Mask ) );
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if( aSkipPlatedPads && isPlated )
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if( aSkipPlatedPads && isPlated )
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continue;
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continue;
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@ -244,7 +244,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
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// Skip vias annulus when not connected on this layer (if removing is enabled)
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// Skip vias annulus when not connected on this layer (if removing is enabled)
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const VIA *via = dyn_cast< const VIA*>( track );
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const VIA *via = dyn_cast< const VIA*>( track );
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if( via && !via->IsPadOnLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
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if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
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continue;
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continue;
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// Add object item to layer container
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// Add object item to layer container
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@ -449,7 +449,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
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// Skip vias annulus when not connected on this layer (if removing is enabled)
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// Skip vias annulus when not connected on this layer (if removing is enabled)
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const VIA *via = dyn_cast< const VIA*>( track );
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const VIA *via = dyn_cast< const VIA*>( track );
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if( via && !via->IsPadOnLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
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if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
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continue;
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continue;
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// Add the track/via contour
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// Add the track/via contour
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@ -126,7 +126,7 @@ void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer,
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if( aLayer != UNDEFINED_LAYER && !pad->IsOnLayer(aLayer) )
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if( aLayer != UNDEFINED_LAYER && !pad->IsOnLayer(aLayer) )
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continue;
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continue;
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if( !pad->IsPadOnLayer( aLayer ) && IsCopperLayer( aLayer ) )
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if( !pad->FlashLayer( aLayer ) && IsCopperLayer( aLayer ) )
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continue;
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continue;
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// NPTH pads are not drawn on layers if the shape size and pos is the same
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// NPTH pads are not drawn on layers if the shape size and pos is the same
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@ -153,8 +153,8 @@ void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer,
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}
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}
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}
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}
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const bool isPlated = ( ( aLayer == F_Cu ) && pad->IsPadOnLayer( F_Mask ) ) ||
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const bool isPlated = ( ( aLayer == F_Cu ) && pad->FlashLayer( F_Mask ) ) ||
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( ( aLayer == B_Cu ) && pad->IsPadOnLayer( B_Mask ) );
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( ( aLayer == B_Cu ) && pad->FlashLayer( B_Mask ) );
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if( aSkipPlatedPads && isPlated )
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if( aSkipPlatedPads && isPlated )
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continue;
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continue;
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@ -181,11 +181,11 @@ bool D_PAD::IsFlipped() const
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}
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}
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bool D_PAD::IsPadOnLayer( LSET aLayers ) const
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bool D_PAD::FlashLayer( LSET aLayers ) const
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{
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{
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for( auto layer : aLayers.Seq() )
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for( auto layer : aLayers.Seq() )
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{
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{
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if( IsPadOnLayer( layer ) )
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if( FlashLayer( layer ) )
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return true;
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return true;
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}
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}
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@ -193,7 +193,7 @@ bool D_PAD::IsPadOnLayer( LSET aLayers ) const
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}
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}
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bool D_PAD::IsPadOnLayer( int aLayer ) const
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bool D_PAD::FlashLayer( int aLayer ) const
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{
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{
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BOARD* board = GetBoard();
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BOARD* board = GetBoard();
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@ -1194,7 +1194,7 @@ double D_PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const
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return HIDE;
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return HIDE;
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// Only draw the pad if at least one of the layers it crosses is being displayed
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// Only draw the pad if at least one of the layers it crosses is being displayed
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if( board && !IsPadOnLayer( board->GetVisibleLayers() ) )
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if( board && !FlashLayer( board->GetVisibleLayers()) )
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return HIDE;
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return HIDE;
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// Netnames will be shown only if zoom is appropriate
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// Netnames will be shown only if zoom is appropriate
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@ -537,8 +537,8 @@ public:
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return m_layerMask[aLayer];
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return m_layerMask[aLayer];
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}
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}
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bool IsPadOnLayer( int aLayer ) const;
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bool FlashLayer( int aLayer ) const;
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bool IsPadOnLayer( LSET aLayers ) const;
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bool FlashLayer( LSET aLayers ) const;
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bool HitTest( const wxPoint& aPosition, int aAccuracy = 0 ) const override;
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bool HitTest( const wxPoint& aPosition, int aAccuracy = 0 ) const override;
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bool HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy = 0 ) const override;
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bool HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy = 0 ) const override;
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@ -137,7 +137,7 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const
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int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
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int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
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{
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{
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if( !IsPadOnLayer( aLayer ) )
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if( !FlashLayer( aLayer ) )
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{
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{
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if( aSource )
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if( aSource )
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*aSource = _( "removed annular ring" );
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*aSource = _( "removed annular ring" );
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@ -466,11 +466,11 @@ void VIA::SanitizeLayers()
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}
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}
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bool VIA::IsPadOnLayer( LSET aLayers ) const
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bool VIA::FlashLayer( LSET aLayers ) const
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{
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{
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for( auto layer : aLayers.Seq() )
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for( auto layer : aLayers.Seq() )
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{
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{
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if( IsPadOnLayer( layer ) )
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if( FlashLayer( layer ) )
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return true;
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return true;
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}
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}
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@ -478,7 +478,7 @@ bool VIA::IsPadOnLayer( LSET aLayers ) const
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}
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}
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bool VIA::IsPadOnLayer( int aLayer ) const
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bool VIA::FlashLayer( int aLayer ) const
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{
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{
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BOARD* board = GetBoard();
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BOARD* board = GetBoard();
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@ -466,14 +466,14 @@ public:
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* @param aLayer Layer to check for connectivity
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* @param aLayer Layer to check for connectivity
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* @return true if connected by pad or track
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* @return true if connected by pad or track
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*/
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*/
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bool IsPadOnLayer( int aLayer ) const;
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bool FlashLayer( int aLayer ) const;
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/**
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/**
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* Checks to see if the via is present on any of the layers in the set
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* Checks to see if the via is present on any of the layers in the set
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* @param aLayers set of layers to check the via against
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* @param aLayers set of layers to check the via against
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* @return true if connected by pad or track on any of the associated layers
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* @return true if connected by pad or track on any of the associated layers
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*/
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*/
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bool IsPadOnLayer( LSET aLayers ) const;
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bool FlashLayer( LSET aLayers ) const;
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/**
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/**
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* Function SetDrill
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* Function SetDrill
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@ -275,7 +275,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testCopperDrawItem( BOARD_ITEM* aItem )
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SHAPE_SEGMENT padCylinder;
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SHAPE_SEGMENT padCylinder;
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const SHAPE* padShape;
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const SHAPE* padShape;
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if( pad->IsPadOnLayer( layer ) )
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if( pad->FlashLayer( layer ) )
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{
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{
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padShape = pad->GetEffectiveShape().get();
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padShape = pad->GetEffectiveShape().get();
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}
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}
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@ -377,7 +377,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I
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SHAPE_SEGMENT padCylinder;
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SHAPE_SEGMENT padCylinder;
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const SHAPE* padShape;
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const SHAPE* padShape;
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if( pad->IsPadOnLayer( aLayer ) )
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if( pad->FlashLayer( aLayer ) )
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{
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{
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padShape = pad->GetEffectiveShape().get();
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padShape = pad->GetEffectiveShape().get();
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}
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}
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@ -465,7 +465,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I
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{
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{
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VIA* via = static_cast<VIA*>( track );
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VIA* via = static_cast<VIA*>( track );
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if( !via->IsPadOnLayer( aLayer ) )
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if( !via->FlashLayer( aLayer ) )
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trackSeg.SetWidth( via->GetDrillValue() );
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trackSeg.SetWidth( via->GetDrillValue() );
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}
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}
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@ -684,7 +684,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx,
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SHAPE_SEGMENT refPadCylinder;
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SHAPE_SEGMENT refPadCylinder;
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const SHAPE* refPadShape;
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const SHAPE* refPadShape;
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if( refPad->IsPadOnLayer( layer ) )
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if( refPad->FlashLayer( layer ) )
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{
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{
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refPadShape = refPad->GetEffectiveShape().get();
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refPadShape = refPad->GetEffectiveShape().get();
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}
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}
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@ -704,7 +704,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx,
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SHAPE_SEGMENT padCylinder;
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SHAPE_SEGMENT padCylinder;
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const SHAPE* padShape;
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const SHAPE* padShape;
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if( pad->IsPadOnLayer( layer ) )
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if( pad->FlashLayer( layer ) )
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{
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{
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padShape = pad->GetEffectiveShape().get();
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padShape = pad->GetEffectiveShape().get();
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}
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}
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@ -640,7 +640,7 @@ void PCB_PAINTER::draw( const VIA* aVia, int aLayer )
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/// Vias not connected to copper are optionally not drawn
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/// Vias not connected to copper are optionally not drawn
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/// We draw instead the hole size to ensure we show the proper clearance
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/// We draw instead the hole size to ensure we show the proper clearance
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if( IsCopperLayer( aLayer ) && !aVia->IsPadOnLayer( aLayer ) )
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if( IsCopperLayer( aLayer ) && !aVia->FlashLayer( aLayer ) )
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radius = getDrillSize(aVia) / 2.0 ;
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radius = getDrillSize(aVia) / 2.0 ;
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bool sketchMode = false;
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bool sketchMode = false;
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@ -200,11 +200,12 @@ void PlotOneBoardLayer( BOARD *aBoard, PLOTTER* aPlotter, PCB_LAYER_ID aLayer,
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}
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}
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/* Plot a copper layer or mask.
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/*
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* Plot a copper layer or mask.
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* Silk screen layers are not plotted here.
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* Silk screen layers are not plotted here.
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*/
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*/
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void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
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void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask,
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LSET aLayerMask, const PCB_PLOT_PARAMS& aPlotOpt )
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const PCB_PLOT_PARAMS& aPlotOpt )
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{
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{
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BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
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BRDITEMS_PLOTTER itemplotter( aPlotter, aBoard, aPlotOpt );
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@ -249,7 +250,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
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}
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}
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/// pads not connected to copper are optionally not drawn
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/// pads not connected to copper are optionally not drawn
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if( onCopperLayer && !pad->IsPadOnLayer( aLayerMask ) )
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if( onCopperLayer && !pad->FlashLayer( aLayerMask ) )
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continue;
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continue;
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COLOR4D color = COLOR4D::BLACK;
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COLOR4D color = COLOR4D::BLACK;
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@ -422,7 +423,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter,
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int diameter = Via->GetWidth() + 2 * via_margin + width_adj;
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int diameter = Via->GetWidth() + 2 * via_margin + width_adj;
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/// Vias not connected to copper are optionally not drawn
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/// Vias not connected to copper are optionally not drawn
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if( onCopperLayer && !Via->IsPadOnLayer( aLayerMask ) )
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if( onCopperLayer && !Via->FlashLayer( aLayerMask ) )
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continue;
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continue;
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// Don't draw a null size item :
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// Don't draw a null size item :
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@ -911,14 +911,14 @@ bool PNS_KICAD_IFACE::IsOnLayer( const PNS::ITEM* aItem, int aLayer )
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{
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{
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const VIA* via = static_cast<const VIA*>( aItem->Parent() );
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const VIA* via = static_cast<const VIA*>( aItem->Parent() );
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return via->IsPadOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
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return via->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ));
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}
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}
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case PCB_PAD_T:
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case PCB_PAD_T:
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{
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{
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const D_PAD* pad = static_cast<const D_PAD*>( aItem->Parent() );
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const D_PAD* pad = static_cast<const D_PAD*>( aItem->Parent() );
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return pad->IsPadOnLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
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return pad->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ));
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}
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}
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default:
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default:
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@ -723,7 +723,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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{
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{
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for( D_PAD* pad : module->Pads() )
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for( D_PAD* pad : module->Pads() )
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{
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{
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if( !pad->IsPadOnLayer( aLayer ) )
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if( !pad->FlashLayer( aLayer ) )
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{
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{
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if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
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if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
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continue;
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continue;
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@ -770,7 +770,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA
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{
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{
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VIA* via = static_cast<VIA*>( track );
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VIA* via = static_cast<VIA*>( track );
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if( !via->IsPadOnLayer( aLayer ) )
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if( !via->FlashLayer( aLayer ) )
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{
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{
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int radius = via->GetDrillValue() / 2 + bds.GetHolePlatingThickness() + gap;
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int radius = via->GetDrillValue() / 2 + bds.GetHolePlatingThickness() + gap;
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TransformCircleToPolygon( aHoles, via->GetPosition(), radius, m_maxError );
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TransformCircleToPolygon( aHoles, via->GetPosition(), radius, m_maxError );
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