Translated using Weblate (Chinese (Simplified))
Currently translated at 86.2% (7891 of 9145 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/
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Hubert Hu
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@ -32,7 +32,7 @@ msgstr ""
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"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
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"Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n"
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"Report-Msgid-Bugs-To: \n"
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"Report-Msgid-Bugs-To: \n"
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"POT-Creation-Date: 2023-12-19 08:33-0800\n"
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"POT-Creation-Date: 2023-12-19 08:33-0800\n"
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"PO-Revision-Date: 2023-12-28 08:09+0000\n"
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"PO-Revision-Date: 2023-12-28 12:05+0000\n"
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"Last-Translator: Hubert Hu <qinghan.hu@gmail.com>\n"
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"Last-Translator: Hubert Hu <qinghan.hu@gmail.com>\n"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"Language-Team: Chinese (Simplified) <https://hosted.weblate.org/projects/"
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"kicad/master-source/zh_Hans/>\n"
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"kicad/master-source/zh_Hans/>\n"
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@ -36786,6 +36786,446 @@ msgid ""
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"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
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"For the full documentation see [https://docs.kicad.org](https://docs.kicad."
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"org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)."
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"org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)."
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msgstr ""
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msgstr ""
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"### Top-level Clauses（顶层语句）\n"
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"\n"
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" (version <number>)\n"
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"\n"
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" (rule <rule_name> <rule_clause> ...)\n"
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"\n"
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"\n"
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"<br>\n"
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"\n"
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"### Rule Clauses（规则语句）\n"
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"\n"
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" (constraint <约束类型> ...)\n"
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"\n"
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" (condition \"<表达式>\")\n"
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"\n"
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" (layer \"<层名>\")\n"
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"\n"
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" (severity <违规等级>)\n"
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"\n"
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"\n"
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"<br>\n"
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"\n"
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"### Constraints（约束）\n"
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"\n"
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"| 约束类型 | 变量类型 "
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" | 描述 "
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" "
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" "
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" "
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" "
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" "
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" |\n"
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"|---------------------------|------------------------------------------------"
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"------------------------------------------------------------------------|----"
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"-----------------------------------------------------------------------------"
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"-----------------------------------------------------------------------------"
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"-----------------------------------------------------------------------------"
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"-----------------------------------------------------------------------------"
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"-----------------------------------------------------------------------------"
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"----------------------------------------------------|\n"
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"| `annular_width` | min/opt/max "
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" | 检"
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"查过孔的孔环宽度<br> "
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" "
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" "
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" "
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" "
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" |\n"
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"| `clearance` | min "
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" | "
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"定义不同网络铜箔对象的 **电气** 间隙。 (如果您想定义不考虑网络的对象的间隙，"
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"请查看 `physical_clearance` 约束类型。<br><br>如果允许铜箔对象重叠(碰撞)，"
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"可以创建一个 `clearance` 约束，并将 `min` 值设为小于零 (例如, `-1`)。<br> "
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" "
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" |\n"
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"| `courtyard_clearance` | min "
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" | "
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"检查封装 Courtyard 之间的间隙，如果任何两个封装之间的距离小于 min "
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"的值，则会产生错误。如果封装没有 Courtyard，则该约束不会产生错误。<br> "
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" "
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" "
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" |\n"
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"| `diff_pair_gap` | min/opt/max "
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" | "
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"检查差分对中耦合走线之间的间隙。 耦合走线是相互平行的线段。 "
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"差分对间隙约束不对差分对的非耦合部分（例如，元件的扇出部分）进行测试。<br> "
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" "
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" "
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" |\n"
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"| `diff_pair_uncoupled` | max "
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" | 检"
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"查差分对正负走线非耦合部分的间距（例如，差分对从元件扇出，或绕过某一物体（如"
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"通孔）的非耦合部分）。<br> "
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" "
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" |\n"
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"| `disallow` | `track`<br>`via`<br>`micro_via`<br>`buried_via`"
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"<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> | "
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"指定一个或多个对象类型不被允许, 使用空格分割。 例如, `(constraint disallow "
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"track)` 或 `(constraint disallow track via pad)`。 "
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"如果这个类型的对象满足规则条件，就会产生一个 DRC 错误。<br><br>该约束类型与 "
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"keepout 规则区域基本相同，但可以创建更具体的 keepout 约束。"
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"<br> |\n"
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"| `edge_clearance` | min/opt/max "
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" | "
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"检查对象与板边的间隙。<br><br>这也可以看作是 \"铣削公差\"，"
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"因为电路板边缘将包括 `Edge.Cuts` 层上的所有图形对象以及任何 *椭圆* 焊盘孔。 "
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"(钻孔公差请查看 `physical_hole_clearance` 约束类型)<br> "
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" "
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" |\n"
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"| `length` | min/max "
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" | "
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"检查符合规则条件的网络的总布线长度，如果网络的长度低于限制条件的 `min` "
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"最小值（如果指定）或高于 `max` 最大值（如果指定），则生成错误。<br> "
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" "
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" "
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" |\n"
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"| `hole` | min/max "
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" | "
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"检查焊盘或过孔中钻孔的大小（直径）。 对于椭圆形孔，较小的直径将与 `min` "
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"最小值（如果指定）对比，较大的直径将与 `max` 最大值（如果指定）对比。<br> "
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" "
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" "
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" |\n"
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"| `hole_clearance` | min "
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" | "
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"检查焊盘或过孔中的钻孔与不同网络的铜箔对象之间的间隙。 "
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"间隙是从孔的直径而不是孔的中心测量的。<br> "
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" "
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" "
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" |"
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"\n"
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"| `hole_to_hole` | min "
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" | "
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"检查焊盘和过孔中机械钻孔之间的间隙。 间隙在孔边缘之间测量，而不是从孔的中心测"
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"量。<br><br>该约束类型完全是为了保护钻头。 不检查 "
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"**激光钻孔**（微孔）与其他非机械钻孔之间的间隙，也不检查 "
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"**铣削孔**（椭圆形）与其他非机械钻孔之间的间隙。<br> |\n"
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"| `physical_clearance` | min "
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" | "
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"检查给定层（包括非铜层）上两个对象之间的间隙。<br><br>虽然这可以执行比 "
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"`clearance` 更通用的检查，但速度要慢得多。 尽可能使用 `clearance` 约束。<br> "
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" "
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" "
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" |\n"
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"| `physical_hole_clearance` | min "
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" | "
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"检查焊盘或过孔中的钻孔与另一个对象之间的间隙，无论它们是否属于同一网络。 "
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"间隙是从孔的边缘而不是中心测量的。<br><br>这也可以被认为是“钻孔公差”，"
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"因为它只包括 **圆** 孔（有关铣削公差，请参阅 `edge_clearance`）。<br> "
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" "
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" |\n"
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"| `silk_clearance` | min/opt/max "
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" | "
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"检查丝印层上的对象与其他对象之间的间隙。<br> "
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" "
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" "
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" "
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" "
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" |\n"
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"| `skew` | max "
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" | "
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"检查所有符合规则条件的网络的 "
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"skew，即符合规则的每个网络的长度与网络总长的平均值之间的差值。 "
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"如果该平均值与任何一个网络的长度之间的差的绝对值高于约束 `max` "
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"最大值，则会产生错误。<br> "
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" |\n"
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"| `thermal_relief_gap` | min "
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" | "
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"指定在热焊盘连接方式下，焊盘与敷铜区域之间的最小间隙。<br> "
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" "
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" "
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" "
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" "
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" |\n"
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"| `thermal_spoke_width` | opt "
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" | "
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"指定在热焊盘连接方式下，连接焊盘与敷铜的辐条的宽度。<br> "
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" "
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" "
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" "
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" "
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" |\n"
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"| `track_width` | min/opt/max "
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" | "
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"检查走线和圆弧走线的宽度。 对于宽度低于 `min` 最小值（如果指定）或高于 `max` "
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"最大值（如果指定）的走线线段，都会生成错误。<br> "
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" "
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" "
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" |\n"
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"| `via_count` | max "
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" | "
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"计算每个与规则条件匹配的网络的过孔数量。 如果该数字超过匹配网络上的约束 `max`"
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" 最大值，则将为该网络生成错误。<br> "
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" "
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" "
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" |\n"
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"| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` "
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" | "
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"指定焊盘与敷铜区域之间的连接方式。<br> "
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" "
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" "
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" "
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" "
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" |\n"
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"\n"
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"\n"
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"### Items（对象）\n"
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"\n"
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" * `A` _第一个（或仅有的）测试对象_\n"
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" * `B` _第二个测试对象（对于需要两个对象的规则）_\n"
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" * `L` _测试的层_\n"
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"\n"
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"<br>\n"
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"\n"
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"### Severity Names（违规级别名称）\n"
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"\n"
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" * warning（警告）\n"
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" * error（错误）\n"
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" * exclusion（排除在外）\n"
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" * ignore（忽略）\n"
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"\n"
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"<br>\n"
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"\n"
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"### 示例\n"
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"\n"
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" (version 1)\n"
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"\n"
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" (rule HV\n"
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" (constraint clearance (min 1.5mm))\n"
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" (condition \"A.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV\n"
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" (layer outer)\n"
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" (constraint clearance (min 1.5mm))\n"
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" (condition \"A.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV_HV\n"
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" # wider clearance between HV tracks\n"
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" (constraint clearance (min \"1.5mm + 2.0mm\"))\n"
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" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n"
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"\n"
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"\n"
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" (rule HV_unshielded\n"
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" (constraint clearance (min 2mm))\n"
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" (condition \"A.NetClass == 'HV' && !A.enclosedByArea('Shield*')\"))\n"
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"\n"
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"\n"
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" (rule heavy_thermals\n"
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" (constraint thermal_spoke_width (min 0.5mm))\n"
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" (condition \"A.NetClass == 'HV'\"))\n"
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"<br><br>\n"
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"\n"
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"### Notes（注意事项）\n"
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"\n"
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"版本语句必须是第一个语句。 \n"
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||||||
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"它表示文件的语法版本，以便未来的规则解析器可以执行自动更新。 "
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"它应该设置为“1”。\n"
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"\n"
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"规则应按具体情况排序。 \n"
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"后面的规则优先于前面的规则； 一旦找到后面匹配的规则，就不会检查之前的规则。\n"
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"\n"
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"使用 Ctrl+/ 对选中的行添加或取消注释。\n"
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||||||
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"<br><br><br>\n"
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"\n"
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"### Expression functions（表达式函数）\n"
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"\n"
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"所有的函数参数支持简单的通配符 (`*` and `?`)。\n"
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"<br><br>\n"
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"\n"
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" A.intersectsCourtyard('<footprint_refdes>')\n"
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"若 `A` 的任何部分落在指定封装的 Courtyard 区域中，则为 True。\n"
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"<br><br>\n"
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"\n"
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" A.intersectsFrontCourtyard('<footprint_refdes>')\n"
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"若 `A` 的任何部分落在指定封装的顶层 Courtyard 区域中，则为 True。\n"
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"<br><br>\n"
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"\n"
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" A.intersectsBackCourtyard('<footprint_refdes>')\n"
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"若 `A` 的任何部分落在指定封装的底层 Courtyard 区域中，则为 True。\n"
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"<br><br>\n"
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"\n"
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" A.intersectsArea('<zone_name>')\n"
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"若 `A` 的任何部分落在指定区域的边框内，则为 True。\n"
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"<br><br>\n"
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"\n"
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" A.enclosedByArea('<zone_name>')\n"
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"若 `A` 完全落在指定区域的边框内，则为 True。\n"
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"\n"
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"注意: 调用该函数比 `intersectsArea()`更费时。尽可能使用 `intersectsArea()`。"
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"\n"
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"<br><br>\n"
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"\n"
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" A.getField('<field_name>')\n"
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"给定字段的值。 只有封装才有字段，因此仅当 `A` 是封装时才返回值。\n"
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"<br><br>\n"
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"\n"
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" A.isPlated()\n"
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"若 `A` 有镀敷孔，则为 True。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" A.inDiffPair('<net_name>')\n"
|
||||||
|
"若 `A` 含有指定差分对的网络，则为 True。 <网络名> "
|
||||||
|
"是指定差分对的基础名称。例如， inDiffPair('CLK') matches items in the CLK_P "
|
||||||
|
"and CLK_N nets. True \n"
|
||||||
|
"`<net_name>` 是差分对的基准名称。 例如, `inDiffPair('/CLK')` "
|
||||||
|
"可以匹配网络对象 `/CLK_P` 及 `/CLK_N`。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" AB.isCoupledDiffPair()\n"
|
||||||
|
"若 `A` 和 `B` 是同一差分对的网络成员，则为 True。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" A.memberOfGroup('<group_name>')\n"
|
||||||
|
"若 `A` 是指定分组的成员，则为 True。组名可以包含通配符。\n"
|
||||||
|
"包含嵌套的分组成员。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" A.memberOfFootprint('<footprint_reference>')\n"
|
||||||
|
"若 `A` 是给定参考位号匹配的封装的成员，则为 True。位号可以包含通配符。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" A.memberOfSheet('<sheet_path>')\n"
|
||||||
|
"若 `A` 是给定路径的原理图的成员，则为 True。原理图路径可以包含通配符。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
" A.existsOnLayer('<layer_name>')\n"
|
||||||
|
"若 `A` 在给定的层上，则为 True。层名称可以是在 “Board Setup > Board Editor "
|
||||||
|
"Layers”中分配的名称\n"
|
||||||
|
"或规范名称（比如 `F.Cu`）。\n"
|
||||||
|
"\n"
|
||||||
|
"注意: 若 `A` 位于给定层上，则返回 True，无论是否正在为该层评估规则。\n"
|
||||||
|
"对于后者，请在规则中使用 `(layer \"layer_name\")` 语句。\n"
|
||||||
|
"<br><br>\n"
|
||||||
|
"\n"
|
||||||
|
"### 更多示例\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"copper keepout\"\n"
|
||||||
|
" (constraint disallow track via zone)\n"
|
||||||
|
" (condition \"A.intersectsArea('zone3')\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"BGA neckdown\"\n"
|
||||||
|
" (constraint track_width (min 0.2mm) (opt 0.25mm))\n"
|
||||||
|
" (constraint clearance (min 0.05mm) (opt 0.08mm))\n"
|
||||||
|
" (condition \"A.intersectsCourtyard('U3')\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 禁止过孔盖油处有丝印\n"
|
||||||
|
" (rule silk_over_via\n"
|
||||||
|
" (constraint silk_clearance (min 0.2mm))\n"
|
||||||
|
" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Distance between Vias of Different Nets\"\n"
|
||||||
|
" (constraint hole_to_hole (min 0.254mm))\n"
|
||||||
|
" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net\"))"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Clearance between Pads of Different Nets\"\n"
|
||||||
|
" (constraint clearance (min 3.0mm))\n"
|
||||||
|
" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net\"))"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Via Hole to Track Clearance\"\n"
|
||||||
|
" (constraint hole_clearance (min 0.254mm))\n"
|
||||||
|
" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Pad to Track Clearance\"\n"
|
||||||
|
" (constraint clearance (min 0.2mm))\n"
|
||||||
|
" (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"clearance-to-1mm-cutout\"\n"
|
||||||
|
" (constraint edge_clearance (min 0.8mm))\n"
|
||||||
|
" (condition \"A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Max Drill Hole Size Mechanical\"\n"
|
||||||
|
" (constraint hole_size (max 6.3mm))\n"
|
||||||
|
" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Max Drill Hole Size PTH\"\n"
|
||||||
|
" (constraint hole_size (max 6.35mm))\n"
|
||||||
|
" (condition \"A.Pad_Type == 'Through-hole'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 为给定的差分对定义最优的（opt）的间距\n"
|
||||||
|
" (rule \"dp clock gap\"\n"
|
||||||
|
" (constraint diff_pair_gap (opt \"0.8mm\"))\n"
|
||||||
|
" (condition \"A.inDiffPair('/CLK')\"))\n"
|
||||||
|
"\n"
|
||||||
|
" # 为任意差分对与周围对象定义一个更大的间距\n"
|
||||||
|
" (rule \"dp clearance\"\n"
|
||||||
|
" (constraint clearance (min \"1.5mm\"))\n"
|
||||||
|
" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 不要在散热焊盘上使用热焊盘的连接方式\n"
|
||||||
|
" (rule heat_sink_pad\n"
|
||||||
|
" (constraint zone_connection solid)\n"
|
||||||
|
" (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n"
|
||||||
|
"\n"
|
||||||
|
" # 要求连接到敷铜有4个散热辐条\n"
|
||||||
|
" (rule fully_spoked_pads\n"
|
||||||
|
" (constraint min_resolved_spokes 4))\n"
|
||||||
|
"\n"
|
||||||
|
" # 为所有的敷铜区域设置热焊盘间隙及辐条宽度\n"
|
||||||
|
" (rule defined_relief\n"
|
||||||
|
" (constraint thermal_relief_gap (min 10mil))\n"
|
||||||
|
" (constraint thermal_spoke_width (min 12mil)))\n"
|
||||||
|
"\n"
|
||||||
|
" # 覆盖 GND 和 PWD 敷铜区域的热焊盘间隙及辐条宽度\n"
|
||||||
|
" (rule defined_relief_pwr\n"
|
||||||
|
" (constraint thermal_relief_gap (min 10mil))\n"
|
||||||
|
" (constraint thermal_spoke_width (min 12mil))\n"
|
||||||
|
" (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 防止焊料从 SMD 焊盘上吸走\n"
|
||||||
|
" (rule holes_in_pads\n"
|
||||||
|
" (constraint physical_hole_clearance (min 0.2mm))\n"
|
||||||
|
" (condition \"B.Pad_Type == 'SMD'\"))\n"
|
||||||
|
"\n"
|
||||||
|
" # 不允许阻焊开窗值被覆盖\n"
|
||||||
|
" (rule \"disallow solder mask margin overrides\"\n"
|
||||||
|
" (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n"
|
||||||
|
" (condition \"A.Type == 'Pad'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 确保元件与电路板边缘之间的机械间隙\n"
|
||||||
|
" (rule front_mechanical_board_edge_clearance\n"
|
||||||
|
" (layer \"F.Courtyard\")\n"
|
||||||
|
" (constraint physical_clearance (min 3mm))\n"
|
||||||
|
" (condition \"B.Layer == 'Edge.Cuts'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 检查承载电流的能力\n"
|
||||||
|
" (rule high-current\n"
|
||||||
|
" (constraint track_width (min 1.0mm))\n"
|
||||||
|
" (constraint connection_width (min 0.8mm))\n"
|
||||||
|
" (condition \"A.NetClass == 'Power'\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
" # 单独的钻头和铣刀尺寸限制\n"
|
||||||
|
" (rule \"Plated through-hole size\"\n"
|
||||||
|
" (constraint hole_size (min 0.2mm) (max 6.35mm))\n"
|
||||||
|
" (condition \"A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y\"))\n"
|
||||||
|
"\n"
|
||||||
|
" (rule \"Plated slot size\"\n"
|
||||||
|
" (constraint hole_size (min 0.5mm))\n"
|
||||||
|
" (condition \"A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y\"))\n"
|
||||||
|
"\n"
|
||||||
|
"\n"
|
||||||
|
"### Documentation（文档）\n"
|
||||||
|
"\n"
|
||||||
|
"更完整的文档请查看 [https://docs.kicad.org](https://docs.kicad.org/"
|
||||||
|
"GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules)."
|
||||||
|
|
||||||
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19
|
#: pcbnew/dialogs/panel_setup_teardrops_base.cpp:19
|
||||||
#, fuzzy
|
#, fuzzy
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue