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Test case for immediate SBCKT models.

This commit is contained in:
Jeff Young 2023-01-21 18:07:06 +00:00
parent 6053b86a24
commit e218c7109b
5 changed files with 1725 additions and 15 deletions
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303
qa/data/eeschema/issue13431.kicad_pro Normal file
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@ -0,0 +1,303 @@
{
"board": {
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "example_for_kicad_6.0.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
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},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
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"drawing": {
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"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
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"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 3,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"95209d8c-a917-4d20-aa13-b6e7ee41be98",
""
]
],
"text_variables": {}
}

1319
qa/data/eeschema/issue13431.kicad_sch Normal file
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File diff suppressed because it is too large Load Diff

67
qa/data/eeschema/issue13431.spice Normal file
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@ -0,0 +1,67 @@
KiCad schematic
.save all
.probe alli
.tran 10us 20ms uic
.option INTERP
.subckt OPAMP INon IInv out Vp Vm g=100k
bGain gain gnd v={g*v(INon, IInv)}
bOut out gnd v={v(gain)> v(Vp) ? v(Vp) : v(gain) < v(Vm) ? v(Vm) : v(gain)}
.ends OPAMP
.subckt SG3525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
* Voltage reference
.param Vref = 5.1V
bVref 16 12 v={Vref < v(15, 12) ? Vref : v(15) }
* Error amplifier (opamp)
xOpampError 2 1 9 15 12 OPAMP
* Measure Ct
aCtMeter 5 CtVal ctest
.model ctest cmeter(gain=1.0)
* Measure Rt
vRtMeasI 16 6 0
bRt 12 RtVal v={-Vref/i(vRtMeasI)}
* Triangular wave oscillator
* f = 1/(Ct*0.7*Rt)
bFreq freq 12 v={(1/(v(CtVal)*0.7*v(RtVal))) < 1 ? 1 : 1/(v(CtVal)*0.7*v(RtVal))}
aTriOsc freq carrier trigen
.model trigen triangle(cntl_array = [10 500e3]
+freq_array=[10 500e3] out_low = 0
+out_high = {Vref} duty_cycle = 0.999)
* Carrier debug (send it to OSC output)
Rtie carrier 4 0
* PWM
bOutA 11 12 v={min(v(9), v(8)) > v(carrier)+v(12) ? v(doShutdown,12) < {Vref/2} ? v(13) : v(12) : v(12) }
bOutB 14 12 v={min(v(9), v(8)) < v(carrier)+v(12) ? v(doShutdown,12) < {Vref/2} ? v(13) : v(12) : v(12) }
* Soft Start
.param IssVal = 50u
Iss 12 8 {IssVal}
a1 12 8 vclamp
.model vclamp zener(v_breakdown={Vref} i_breakdown={IssVal})
*.model vclamp sidiode(Vrev={Vref})
* Shutdown
bShutdown doShutdown 12 v={v(10,12) > 0.8 ? {Vref} : v(12) }; Threshold on pin 10 is around 0.8V
sShutdownSwitch 8 12 doShutdown 12 sswitch ON
.model sswitch SW(RON=3k VT={Vref/2})
.ends SG3525
C4 /ct GND 150n
R1 /rt GND 3.22k
C3 +15V GND 100n
XU1 /opamp_buff_fb Net-_U1-NI_ unconnected-_U1-SYNC-Pad3_ unconnected-_U1-OSC-Pad4_ /ct /rt /ct /soft_start /opamp_buff_fb GND /pwm_to_driver GND +15V unconnected-_U1-OUTB-Pad14_ +15V /vref SG3525
C1 /vref GND 100n
V3 Net-_U1-NI_ GND 4.5
V1 +15V GND 15
V2 GND -15V 15
C2 /soft_start GND 100n
.end

12
qa/unittests/eeschema/eeschema_test_utils.h
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@ -1,7 +1,7 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2019-2022 KiCad Developers, see AUTHORS.TXT for contributors.
* Copyright (C) 2019-2023 KiCad Developers, see AUTHORS.TXT for contributors.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -64,8 +64,7 @@ public:
: m_schematic( nullptr ),
m_pi( SCH_IO_MGR::FindPlugin( SCH_IO_MGR::SCH_KICAD ) ),
m_manager( true )
{
}
{ }
virtual ~SCHEMATIC_TEST_FIXTURE()
{
@ -77,11 +76,8 @@ protected:
virtual void LoadSchematic( const wxString& aRelativePath );
virtual wxFileName GetSchematicPath( const wxString& aBaseName );
///> Schematic to load
SCHEMATIC m_schematic;
SCH_PLUGIN* m_pi;
SCHEMATIC m_schematic;
SCH_PLUGIN* m_pi;
SETTINGS_MANAGER m_manager;
};

39
qa/unittests/eeschema/sim/test_sim_regressions.cpp
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@ -63,22 +63,47 @@ public:
netFile.SetExt( "spice" );
return netFile.GetFullPath();
}
unsigned GetNetlistOptions() override
{
unsigned options = NETLIST_EXPORTER_SPICE::OPTION_ADJUST_INCLUDE_PATHS
| NETLIST_EXPORTER_SPICE::OPTION_SIM_COMMAND;
if( m_SaveCurrents )
options |= NETLIST_EXPORTER_SPICE::OPTION_SAVE_ALL_CURRENTS;
if( m_SaveVoltages )
options |= NETLIST_EXPORTER_SPICE::OPTION_SAVE_ALL_VOLTAGES;
return options;
}
public:
bool m_SaveVoltages = true;
bool m_SaveCurrents = true;
};
BOOST_FIXTURE_TEST_SUITE( SimRegressions, TEST_SIM_REGRESSIONS_FIXTURE )
BOOST_AUTO_TEST_CASE( WindowsPaths )
BOOST_FIXTURE_TEST_CASE( WindowsPaths, TEST_SIM_REGRESSIONS_FIXTURE )
{
LOCALE_IO dummy;
TestNetlist( "issue13591" );
TestTranPoint( 100e-6, { { "I(R1)", 0 }, { "I(R2)", 0 } } );
TestTranPoint( 500e-6, { { "I(R1)", 0 }, { "I(R2)", 0 } } );
TestTranPoint( 100e-6, { { "I(R1)", 0 }, { "I(R2)", 0 } }, 0.00001 );
TestTranPoint( 500e-6, { { "I(R1)", 0 }, { "I(R2)", 0 } }, 0.00001 );
}
BOOST_AUTO_TEST_SUITE_END()
BOOST_FIXTURE_TEST_CASE( ImmediateSBCKTs, TEST_SIM_REGRESSIONS_FIXTURE )
{
LOCALE_IO dummy;
m_SaveCurrents = false;
TestNetlist( "issue13431" );
TestTranPoint( 0.005, { { "V(/soft_start)", 2.489 } }, 0.001 );
TestTranPoint( 0.012, { { "V(/soft_start)", 5.100 } }, 0.001 );
}
#endif // KICAD_SPICE