add IBIS demo, based on schematic/models by Fabien Corona

This commit is contained in:
Graham Keeth 2023-12-03 15:03:45 -05:00 committed by Seth Hillbrand
parent 5af9d3395e
commit e3eab57133
4 changed files with 5772 additions and 0 deletions

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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
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"pin_map": [
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"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "ibis.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
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"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"name": "Grouped By Value",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": "ibis.wbk"
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"1a8e7370-b668-4162-803f-e7f4a10f2245",
"Root"
]
],
"text_variables": {}
}

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{
"last_sch_text_sim_command": "",
"tabs": [
{
"analysis": "TRAN",
"commands": [
".tran 1n 2u\n",
".kicad adjustpaths",
".save all",
".probe alli",
".probe allp"
],
"dottedSecondary": false,
"margins": {
"bottom": 45,
"left": 70,
"right": 70,
"top": 30
},
"measurements": [],
"showGrid": true,
"traces": [
{
"color": "rgb(228, 26, 28)",
"signal": "V(HIGHZ_OUTPUT)",
"trace_type": 1
},
{
"color": "rgb(55, 126, 184)",
"signal": "V(HIGH_OUTPUT)",
"trace_type": 1
},
{
"color": "rgb(77, 175, 74)",
"signal": "V(LOW_OUTPUT)",
"trace_type": 1
},
{
"color": "rgb(152, 78, 163)",
"signal": "V(PRBS_OUTPUT)",
"trace_type": 1
},
{
"color": "rgb(255, 127, 0)",
"signal": "V(PULSE_INPUT)",
"trace_type": 1
},
{
"color": "rgb(255, 255, 51)",
"signal": "V(RECT_OUTPUT)",
"trace_type": 1
}
]
}
],
"user_defined_signals": [],
"version": 6
}

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[IBIS Ver] 1.1 |Let's test a comment
[Comment char] #_char
[File name] ibis_v1_1.ibs
[File Rev] 1.0 #Let's test a comment
[Date] 26/08/2021
[Source] This is the
source for the files
[Notes] We can have some
Notes
[Disclaimer] This is NOT a valid component.
[Component] Virtual
[Manufacturer] KiCad
[Package]
R_pkg 50m 40m 60m
L_pkg 2n NA NA
C_pkg 10p NA NA
[Pin] signal_name model_name R_pin L_pin C_pin
1 VCC POWER 5mm 2n NA
2 GND GND 55m NA NA
3 X Input 55m NA 0.2p
4 Y Output 55m 2n 0.2p
[Model] Input
Model_type Input
Polarity Non-Inverting
Enable Active-High
Vinl = 0.8V
Vinh = 2.0V
C_comp 1.0pF 0.5pF 2.0pF
[Voltage range] 5.0V 4.5V 5.5V
[GND_clamp]
#
# Voltage I(typ) I(min) I(max)
#
-5.0V -50.0m NA NA
0.0V 0 NA NA
5.0V 0 NA NA
[POWER_clamp]
#
# Voltage I(typ) I(min) I(max)
#
-5.0V 50.0m NA NA
0.0V 0 NA NA
5.0V 0 NA NA
[Model] Output
Model_type Output
Polarity Non-Inverting
Enable Active-High
C_comp 10.0pF 8.0pF 15.0pF
[Voltage range] 5.0V 4.5V 5.5V
[Pulldown]
# Voltage I(typ) I(min) I(max)
#
-5.0V -50.0m -40.0m -60.0m
0.0V 0 0 0
5.0V 500.0m 400.0m 600.0m
10.0V 550.0m 440.0m 660.0m
[Pullup]
#
# Voltage I(typ) I(min) I(max)
#
-5.0V 50.0m 40.0m 60.0m
0.0V 0 0 0
5.0V -500.0m -400.0m -600.0m
10.0V -550.0m -440.0m -660.0m
[GND_clamp]
#
# Voltage I(typ) I(min) I(max)
#
-5.0V -500.0m NA NA
-0.7V 0 NA NA
5.0V 0 NA NA
[POWER_clamp]
#
# Voltage I(typ) I(min) I(max)
#
-5.0V 500.0m NA NA
-0.7V 0 NA NA
5.0V 0 NA NA
[Ramp]
# variable typ min max
dV/dt_r 3.0/30n 2.8/30n NA
dV/dt_f 3.0/20n 2.8/20n 3.2/20n
[END]