Update demo
This commit is contained in:
jean-pierre charras
parent
a52dc57887
commit
e7adb92930
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@ -1,104 +1,96 @@
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(module 40tex-Ell600 (layer F.Cu) (tedit 5A29799A)
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(module "40tex-Ell600" (layer F.Cu) (tedit 5D80A46D)
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(descr "Support TEXTOOL Dil 40 pins, pads elliptiques, e=600 mils")
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(tags DEV)
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(fp_text reference 40tex-Ell600 (at -3.81 -3.175) (layer F.SilkS)
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(tags "DEV")
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(fp_text reference "40tex-Ell600" (at -3.81 -3.175) (layer F.SilkS)
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(effects (font (size 2.032 1.27) (thickness 0.3048)))
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)
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(fp_text value VAL*** (at -5.715 1.905) (layer F.SilkS)
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(fp_text value "VAL***" (at -5.715 1.905) (layer F.SilkS)
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(effects (font (size 2.032 1.27) (thickness 0.3048)))
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)
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(pad 1 thru_hole oval (at -24.13 7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
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(pad HOLE thru_hole circle (at 21.59 13.97) (size 2.8 2.8) (drill 2) (layers *.Cu *.Mask))
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(model Sockets.3dshapes/40tex600.wrl
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
(pad "35" thru_hole oval (at -11.43 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "36" thru_hole oval (at -13.97 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "37" thru_hole oval (at -16.51 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "38" thru_hole oval (at -19.05 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "39" thru_hole oval (at -21.59 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "40" thru_hole rect (at -24.13 -7.62) (size 1.6 2.8) (drill 1) (layers *.Cu *.Mask))
|
||||
(pad "HOLE" thru_hole circle (at -26.67 -13.97) (size 2.8 2.8) (drill 2) (layers *.Cu *.Mask))
|
||||
(pad "HOLE" thru_hole circle (at 21.59 13.97) (size 2.8 2.8) (drill 2) (layers *.Cu *.Mask))
|
||||
(model "Sockets.3dshapes/40tex600.wrl"
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
update=21/11/2017 20:47:02
|
||||
update=17/09/2019 13:28:31
|
||||
last_client=kicad
|
||||
[common]
|
||||
NetDir=
|
||||
|
|
@ -9,26 +9,249 @@ NetIExt=net
|
|||
EquName1=devcms
|
||||
[general]
|
||||
version=1
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=pic_programmer.net
|
||||
UseCmpFile=0
|
||||
PadDrill=0.8128
|
||||
PadDrillOvalY=0.8128
|
||||
PadSizeH=1.5748
|
||||
PadSizeV=2.794
|
||||
PcbTextSizeV=2.032
|
||||
PcbTextSizeH=1.524
|
||||
PcbTextThickness=0.3048
|
||||
ModuleTextSizeV=1.524
|
||||
ModuleTextSizeH=1.524
|
||||
ModuleTextSizeThickness=0.3048
|
||||
LastSTEPExportPath=
|
||||
LastIDFExportPath=
|
||||
LastVRMLExportPath=
|
||||
LastSpecctraDSNExportPath=
|
||||
LastGenCADExportPath=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.25
|
||||
MinViaDiameter=0.8999999999999999
|
||||
MinViaDrill=0.5
|
||||
MinMicroViaDiameter=0.508
|
||||
MinMicroViaDrill=0.127
|
||||
MinHoleToHole=0.25
|
||||
CopperEdgeClearance=0.01
|
||||
TrackWidth1=0.5
|
||||
TrackWidth2=0.4
|
||||
TrackWidth3=0.5
|
||||
ViaDiameter1=1.6
|
||||
ViaDrill1=0.6
|
||||
dPairWidth1=0.25
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.381
|
||||
SilkTextSizeV=1.524
|
||||
SilkTextSizeH=1.524
|
||||
SilkTextSizeThickness=0.3048
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.381
|
||||
CopperTextSizeV=2.032
|
||||
CopperTextSizeH=1.524
|
||||
CopperTextThickness=0.3048
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.381
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.09999999999999999
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.09999999999999999
|
||||
SolderMaskMinWidth=0
|
||||
DrawSegmentWidth=0.381
|
||||
BoardOutlineThickness=0.381
|
||||
ModuleOutlineThickness=0.381
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=top_layer
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=bottom_layer
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.25
|
||||
TrackWidth=0.5
|
||||
ViaDiameter=1.6
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.127
|
||||
dPairWidth=0.25
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=POWER
|
||||
Clearance=0.28
|
||||
TrackWidth=0.8
|
||||
ViaDiameter=1.6
|
||||
ViaDrill=0.6
|
||||
uViaDiameter=0.508
|
||||
uViaDrill=0.127
|
||||
dPairWidth=0.28
|
||||
dPairGap=0.28
|
||||
dPairViaGap=0.25
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
EESchema Schematic File Version 5
|
||||
LIBS:pic_programmer-cache
|
||||
EELAYER 29 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
@ -13,6 +13,11 @@ Comment1 ""
|
|||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
5700 1250 6100 1250
|
||||
|
|
@ -420,14 +425,6 @@ F3 "CLOCK-RB6" I L 9200 4150 60
|
|||
F4 "DATA-RB7" I L 9200 3850 60
|
||||
F5 "VCC_PIC" I L 9200 3200 60
|
||||
$EndSheet
|
||||
Text Label 1850 3800 0 60 ~ 0
|
||||
DTR
|
||||
Text Label 1850 3700 0 60 ~ 0
|
||||
CTS
|
||||
Text Label 1850 3600 0 60 ~ 0
|
||||
TXD
|
||||
Text Label 1850 3500 0 60 ~ 0
|
||||
RTS
|
||||
Text Notes 850 6500 0 60 ~ 0
|
||||
8 to 15V
|
||||
NoConn ~ 6750 5150
|
||||
|
|
@ -1527,4 +1524,12 @@ Connection ~ 8800 5150
|
|||
Connection ~ 8000 6100
|
||||
Connection ~ 7450 6100
|
||||
Connection ~ 5450 1500
|
||||
Text Notes 1850 3500 0 60 ~ 0
|
||||
RTS
|
||||
Text Notes 1850 3600 0 60 ~ 0
|
||||
TXD
|
||||
Text Notes 1850 3700 0 60 ~ 0
|
||||
CTS
|
||||
Text Notes 1850 3800 0 60 ~ 0
|
||||
DTR
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
EESchema Schematic File Version 5
|
||||
LIBS:pic_programmer-cache
|
||||
EELAYER 29 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
@ -13,6 +13,11 @@ Comment1 ""
|
|||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
Comment5 ""
|
||||
Comment6 ""
|
||||
Comment7 ""
|
||||
Comment8 ""
|
||||
Comment9 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
3300 6600 3300 6500
|
||||
|
|
|
|||
Loading…
Reference in New Issue