Update demo

This commit is contained in:
jean-pierre charras 2019-09-17 18:54:06 +02:00
parent a52dc57887
commit e7adb92930
6 changed files with 1589 additions and 2763 deletions

View File

@ -1,104 +1,96 @@
(module 40tex-Ell600 (layer F.Cu) (tedit 5A29799A) (module "40tex-Ell600" (layer F.Cu) (tedit 5D80A46D)
(descr "Support TEXTOOL Dil 40 pins, pads elliptiques, e=600 mils") (descr "Support TEXTOOL Dil 40 pins, pads elliptiques, e=600 mils")
(tags DEV) (tags "DEV")
(fp_text reference 40tex-Ell600 (at -3.81 -3.175) (layer F.SilkS) (fp_text reference "40tex-Ell600" (at -3.81 -3.175) (layer F.SilkS)
(effects (font (size 2.032 1.27) (thickness 0.3048))) (effects (font (size 2.032 1.27) (thickness 0.3048)))
) )
(fp_text value VAL*** (at -5.715 1.905) (layer F.SilkS) (fp_text value "VAL***" (at -5.715 1.905) (layer F.SilkS)
(effects (font (size 2.032 1.27) (thickness 0.3048))) (effects (font (size 2.032 1.27) (thickness 0.3048)))
) )
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SolderMaskMinWidth=0 SolderMaskMinWidth=0
DrawSegmentWidth=0.381 SolderPasteClearance=0
BoardOutlineThickness=0.381 SolderPasteRatio=-0
ModuleOutlineThickness=0.381 [pcbnew/Layer.F.Cu]
[eeschema] Name=top_layer
version=1 Type=0
LibDir= Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=bottom_layer
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.25
TrackWidth=0.5
ViaDiameter=1.6
ViaDrill=0.6
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.25
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=POWER
Clearance=0.28
TrackWidth=0.8
ViaDiameter=1.6
ViaDrill=0.6
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.28
dPairGap=0.28
dPairViaGap=0.25

View File

@ -1,6 +1,6 @@
EESchema Schematic File Version 5 EESchema Schematic File Version 5
LIBS:pic_programmer-cache LIBS:pic_programmer-cache
EELAYER 29 0 EELAYER 30 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
@ -13,6 +13,11 @@ Comment1 ""
Comment2 "" Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
Comment5 ""
Comment6 ""
Comment7 ""
Comment8 ""
Comment9 ""
$EndDescr $EndDescr
Wire Wire Line Wire Wire Line
5700 1250 6100 1250 5700 1250 6100 1250
@ -420,14 +425,6 @@ F3 "CLOCK-RB6" I L 9200 4150 60
F4 "DATA-RB7" I L 9200 3850 60 F4 "DATA-RB7" I L 9200 3850 60
F5 "VCC_PIC" I L 9200 3200 60 F5 "VCC_PIC" I L 9200 3200 60
$EndSheet $EndSheet
Text Label 1850 3800 0 60 ~ 0
DTR
Text Label 1850 3700 0 60 ~ 0
CTS
Text Label 1850 3600 0 60 ~ 0
TXD
Text Label 1850 3500 0 60 ~ 0
RTS
Text Notes 850 6500 0 60 ~ 0 Text Notes 850 6500 0 60 ~ 0
8 to 15V 8 to 15V
NoConn ~ 6750 5150 NoConn ~ 6750 5150
@ -1527,4 +1524,12 @@ Connection ~ 8800 5150
Connection ~ 8000 6100 Connection ~ 8000 6100
Connection ~ 7450 6100 Connection ~ 7450 6100
Connection ~ 5450 1500 Connection ~ 5450 1500
Text Notes 1850 3500 0 60 ~ 0
RTS
Text Notes 1850 3600 0 60 ~ 0
TXD
Text Notes 1850 3700 0 60 ~ 0
CTS
Text Notes 1850 3800 0 60 ~ 0
DTR
$EndSCHEMATC $EndSCHEMATC

View File

@ -1,6 +1,6 @@
EESchema Schematic File Version 5 EESchema Schematic File Version 5
LIBS:pic_programmer-cache LIBS:pic_programmer-cache
EELAYER 29 0 EELAYER 30 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
@ -13,6 +13,11 @@ Comment1 ""
Comment2 "" Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
Comment5 ""
Comment6 ""
Comment7 ""
Comment8 ""
Comment9 ""
$EndDescr $EndDescr
Wire Wire Line Wire Wire Line
3300 6600 3300 6500 3300 6600 3300 6500