Eagle SCH import: handle implicit connections
Each named power input pin in Eagle creates an implicit connection to a net with the name of the pin (e.g. GND, VCC). It is also done for the units (gates in Eagle nomenclature) that have not been instantiated in the schematics. To emulate this behaviour in KiCad: - Placed components are checked for power input pins, so they will have global net labels attached to create the described implicit connections. - As the components are placed, the remaining units of the symbol are checked for power inputs to see if they need to be instantiated together with global net labels. Fixes: lp:1755191 * https://bugs.launchpad.net/kicad/+bug/1755191
This commit is contained in:
Maciej Suminski
parent
78c9b34b5d
commit
e7ed415930
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@ -107,6 +107,13 @@ static EDA_RECT getSheetBbox( SCH_SHEET* aSheet )
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}
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///> Extracts the net name part from a pin name (e.g. return 'GND' for pin named 'GND@2')
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static inline wxString extractNetName( const wxString& aPinName )
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{
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return aPinName.BeforeFirst( '@' );
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}
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wxString SCH_EAGLE_PLUGIN::getLibName()
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{
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if( m_libName.IsEmpty() )
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@ -590,6 +597,57 @@ void SCH_EAGLE_PLUGIN::loadSchematic( wxXmlNode* aSchematicNode )
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sheetNode = sheetNode->GetNext();
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}
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}
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// Handle the missing component units that need to be instantiated
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// to create the missing implicit connections
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// Calculate the already placed items bounding box and the page size to determine
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// placement for the new components
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wxSize pageSizeIU = m_rootSheet->GetScreen()->GetPageSettings().GetSizeIU();
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EDA_RECT sheetBbox = getSheetBbox( m_rootSheet );
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wxPoint newCmpPosition( sheetBbox.GetLeft(), sheetBbox.GetBottom() );
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int maxY = sheetBbox.GetY();
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SCH_SHEET_PATH sheetpath;
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m_rootSheet->LocatePathOfScreen( m_rootSheet->GetScreen(), &sheetpath );
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for( auto& cmp : m_missingCmps )
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{
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const SCH_COMPONENT* origCmp = cmp.second.cmp;
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for( auto unitEntry : cmp.second.units )
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{
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if( unitEntry.second == false )
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continue; // unit has been already processed
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// Instantiate the missing component unit
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int unit = unitEntry.first;
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const wxString& reference = origCmp->GetField( REFERENCE )->GetText();
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std::unique_ptr<SCH_COMPONENT> component( new SCH_COMPONENT( *origCmp ) );
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component->SetUnitSelection( &sheetpath, unit );
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component->SetUnit( unit );
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component->SetTimeStamp( EagleModuleTstamp( reference, origCmp->GetField( VALUE )->GetText(), unit ) );
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component->SetOrientation( 0 );
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component->AddHierarchicalReference( sheetpath.Path(), reference, unit );
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// Calculate the placement position
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EDA_RECT cmpBbox = component->GetBoundingBox();
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int posY = newCmpPosition.y + cmpBbox.GetHeight();
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component->SetPosition( wxPoint( newCmpPosition.x, posY ) );
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newCmpPosition.x += cmpBbox.GetWidth();
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maxY = std::max( maxY, posY );
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if( newCmpPosition.x >= pageSizeIU.GetWidth() ) // reached the page boundary?
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newCmpPosition = wxPoint( sheetBbox.GetLeft(), maxY ); // then start a new row
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// Add the global net labels to recreate the implicit connections
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addImplicitConnections( component.get(), m_rootSheet->GetScreen(), false );
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m_rootSheet->GetScreen()->Append( component.release() );
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}
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}
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m_missingCmps.clear();
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}
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@ -735,6 +793,15 @@ void SCH_EAGLE_PLUGIN::loadSheet( wxXmlNode* aSheetNode, int aSheetIndex )
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item->SetPosition( item->GetPosition() + translation );
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item->ClearFlags();
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}
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// Add global net labels for the named power input pins in this sheet
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for( SCH_ITEM* item = m_currentSheet->GetScreen()->GetDrawItems(); item; item = item->Next() )
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{
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if( item->Type() != SCH_COMPONENT_T )
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continue;
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addImplicitConnections( static_cast<SCH_COMPONENT*>( item ), m_currentSheet->GetScreen(), true );
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}
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}
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@ -2400,3 +2467,71 @@ const SEG* SCH_EAGLE_PLUGIN::SEG_DESC::LabelAttached( const SCH_TEXT* aLabel ) c
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return nullptr;
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}
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void SCH_EAGLE_PLUGIN::addImplicitConnections( SCH_COMPONENT* aComponent,
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SCH_SCREEN* aScreen, bool aUpdateSet )
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{
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auto& schLibTable = *m_kiway->Prj().SchSymbolLibTable();
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wxCHECK( aComponent->Resolve( schLibTable ), /*void*/ );
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aComponent->UpdatePinCache();
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auto partRef = aComponent->GetPartRef().lock();
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wxCHECK( partRef, /*void*/ );
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// Normally power parts also have power input pins,
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// but they already force net names on the attached wires
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if( partRef->IsPower() )
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return;
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int unit = aComponent->GetUnit();
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const wxString& reference = aComponent->GetField( REFERENCE )->GetText();
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std::vector<LIB_PIN*> pins;
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partRef->GetPins( pins );
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std::set<int> missingUnits;
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// Search all units for pins creating implicit connections
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for( const auto& pin : pins )
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{
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if( pin->GetType() == PIN_POWER_IN )
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{
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if( !unit || pin->GetUnit() == unit )
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{
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// Create a net label to force the net name on the pin
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SCH_GLOBALLABEL* netLabel = new SCH_GLOBALLABEL;
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netLabel->SetPosition( aComponent->GetPinPhysicalPosition( pin ) );
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netLabel->SetText( extractNetName( pin->GetName() ) );
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netLabel->SetTextSize( wxSize( 10, 10 ) );
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netLabel->SetLabelSpinStyle( 0 );
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aScreen->Append( netLabel );
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}
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else if( aUpdateSet )
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{
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// Found a pin creating implicit connection information in another unit.
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// Such units will be instantiated if they do not appear in another sheet and
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// processed later.
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wxASSERT( pin->GetUnit() );
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missingUnits.insert( pin->GetUnit() );
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}
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}
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}
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if( aUpdateSet )
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{
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auto cmpIt = m_missingCmps.find( reference );
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// Set the flag indicating this unit has been processed
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if( cmpIt != m_missingCmps.end() )
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cmpIt->second.units[unit] = false;
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// Save the units that need later processing
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else if( !missingUnits.empty() )
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{
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EAGLE_MISSING_CMP& entry = m_missingCmps[reference];
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entry.cmp = aComponent;
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for( int i : missingUnits )
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entry.units.emplace( i, true );
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}
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}
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}
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@ -208,6 +208,43 @@ private:
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///> Segments representing wires for intersection checking
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std::vector<SEG_DESC> m_segments;
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// Structure describing missing units containing pins creating implicit connections
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// (named power pins in Eagle).
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struct EAGLE_MISSING_CMP
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{
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EAGLE_MISSING_CMP( const SCH_COMPONENT* aComponent = nullptr )
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: cmp( aComponent )
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{
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}
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///> Link to the parent component
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const SCH_COMPONENT* cmp;
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/* Map of the component units: for each unit there is a flag saying
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* whether the unit needs to be instantiated with appropriate net labels to
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* emulate implicit connections as is done in Eagle.
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*/
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std::map<int, bool> units;
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};
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///> Map references to missing component units data
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std::map<wxString, EAGLE_MISSING_CMP> m_missingCmps;
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/**
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* Creates net labels to emulate implicit connections in Eagle.
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*
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* Each named power input pin creates an implicit connection in Eagle. To emulate this behavior
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* one needs to attach global net labels to the mentioned pins. This is is also expected for the
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* units that are not instantiated in the schematics, therefore such units need to be stored
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* in order to create them at later stage.
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*
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* @param aComponent is the component to process.
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* @param aScreen is the screen where net labels should be added.
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* @param aUpdateSet decides whether the missing units data should be updated.
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*/
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void addImplicitConnections( SCH_COMPONENT* aComponent, SCH_SCREEN* aScreen, bool aUpdateSet );
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};
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#endif // _SCH_EAGLE_PLUGIN_H_
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