Fixed some compilation warnings. Missing features so far: single-module ratsnest & DRC unconnected report
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@ -142,19 +142,6 @@ void NETINFO_LIST::AppendNet( NETINFO_ITEM* aNewElement )
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}
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/* sort function, to sort pad list by netnames
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* this is a case sensitive sort.
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* DO NOT change it because NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname )
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* when search a net by its net name does a binary search
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* and expects to have a nets list sorted by an alphabetic case sensitive sort
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*/
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static bool padlistSortByNetnames( const D_PAD* a, const D_PAD* b )
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{
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return ( a->GetNetname().Cmp( b->GetNetname() ) ) < 0;
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}
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/**
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* Compute and update the net_codes for PADS et and equipots (.m_NetCode member)
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* net_codes are >= 1 (net_code = 0 means not connected)
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@ -169,10 +156,6 @@ static bool padlistSortByNetnames( const D_PAD* a, const D_PAD* b )
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*/
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void NETINFO_LIST::buildListOfNets()
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{
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D_PAD* pad;
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int nodes_count = 0;
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// Restore the initial state of NETINFO_ITEMs
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for( NETINFO_LIST::iterator net( begin() ), netEnd( end() ); net != netEnd; ++net )
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net->Clear();
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@ -350,6 +350,10 @@ const std::list<BOARD_CONNECTED_ITEM*> CONNECTIVITY_DATA::GetConnectedItems(
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const std::list<BOARD_CONNECTED_ITEM*> CONNECTIVITY_DATA::GetNetItems( int aNetCode,
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const KICAD_T aTypes[] ) const
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{
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std::list<BOARD_CONNECTED_ITEM*> rv;
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// FIXME!
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return rv;
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}
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@ -552,8 +552,6 @@ void DRC::testUnconnected()
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connectivity->CheckConnectivity( report );
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printf("Connectivity: %d unconnected\n", report.size());
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for( auto ent : report )
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{
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/* DRC_ITEM* uncItem = new DRC_ITEM( DRCE_UNCONNECTED_PADS,
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@ -1110,4 +1108,3 @@ bool DRC::doFootprintOverlappingDrc()
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return success;
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}
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@ -221,8 +221,6 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC )
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void PCB_EDIT_FRAME::Show_1_Ratsnest( EDA_ITEM* item, wxDC* DC )
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{
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D_PAD* pt_pad = NULL;
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MODULE* Module = NULL;
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if( GetBoard()->IsElementVisible( LAYER_RATSNEST ) )
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return;
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@ -269,9 +269,6 @@ TRACK* PCB_EDIT_FRAME::Begin_Route( TRACK* aTrack, wxDC* aDC )
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newTrack->SetFlags( IS_NEW );
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newTrack->SetState( BEGIN_ONPAD | END_ONPAD, false );
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D_PAD* pad = GetBoard()->GetPad( previousTrack, ENDPOINT_END );
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newTrack->start = previousTrack->end;
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DBG( g_CurrentTrackList.VerifyListIntegrity(); );
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@ -945,7 +945,11 @@ void SELECTION_TOOL::selectAllItemsOnSheet( wxString& aSheetpath )
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std::list<BOARD_CONNECTED_ITEM*> localConnectionList;
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for( int netCode : netcodeList )
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{
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//ratsnest->GetNetItems( netCode, localConnectionList, (RN_ITEM_TYPE)( RN_TRACKS | RN_VIAS ) );
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KICAD_T types[] = { PCB_TRACE_T, PCB_VIA_T, EOT };
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for( auto item : board()->GetConnectivity()->GetNetItems( netCode, types ) )
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{
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localConnectionList.push_back( item );
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}
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}
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for( BOARD_ITEM* i : modList )
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@ -142,8 +142,8 @@ static bool TestForExistingItem( BOARD* aPcb, BOARD_ITEM* aItem )
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itemsList.push_back( item );
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// Append drawings
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for( auto item : aPcb->Drawings() )
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itemsList.push_back( item );
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for( auto ditem : aPcb->Drawings() )
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itemsList.push_back( ditem );
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// Append zones outlines
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for( int ii = 0; ii < aPcb->GetAreaCount(); ii++ )
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@ -565,7 +565,7 @@ void PCB_BASE_EDIT_FRAME::PutDataInPreviousState( PICKED_ITEMS_LIST* aList, bool
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if( IsGalCanvasActive() )
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{
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connectivity->RecalculateRatsnest();
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connectivity->RecalculateRatsnest();
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}
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}
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}
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