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Tighten DRC epsilon value until we decide what to do about it.

This commit is contained in:
Jeff Young 2020-06-04 18:28:08 +01:00
parent c27ca90c13
commit f4d8c30f9a
3 changed files with 20 additions and 14 deletions
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11
include/board_design_settings.h
View File

@ -83,6 +83,10 @@
#define MINIMUM_ERROR_SIZE_MM 0.001
#define MAXIMUM_ERROR_SIZE_MM 0.1
#define DRC_EPSILON 5; // An epsilon to account for rounding errors, etc.
// 5nm is small enough not to materially violate
// any constraints.
/**
* Struct VIA_DIMENSION
* is a small helper container to handle a stock of specific vias each with
@ -849,6 +853,13 @@ public:
inline int GetBoardThickness() const { return m_boardThickness; }
inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
/*
* Function GetDRCEpsilon
* an epsilon which accounts for rounding errors, etc. While currently a global, going
* through this API allows us to easily change it to board-specific if so desired.
*/
int GetDRCEpsilon() const { return DRC_EPSILON; }
/**
* Function GetLineThickness
* Returns the default graphic segment thickness from the layer class for the given layer.

16
pcbnew/drc/drc.cpp
View File

@ -1210,9 +1210,7 @@ bool DRC::doPadToPadsDrc( BOARD_COMMIT& aCommit, D_PAD* aRefPad, D_PAD** aStart,
{
const static LSET all_cu = LSET::AllCuMask();
// Allow an epsilon at least as great as our allowed polygonisation error.
int epsilon = m_pcb->GetDesignSettings().m_MaxError;
LSET layerMask = aRefPad->GetLayerSet() & all_cu;
LSET layerMask = aRefPad->GetLayerSet() & all_cu;
// For hole testing we use a dummy pad which is given the shape of the hole. Note that
// this pad must have a parent because some functions expect a non-null parent to find
@ -1347,7 +1345,7 @@ bool DRC::doPadToPadsDrc( BOARD_COMMIT& aCommit, D_PAD* aRefPad, D_PAD** aStart,
}
int minClearance = aRefPad->GetClearance( pad, &m_clearanceSource );
int clearanceAllowed = minClearance - epsilon;
int clearanceAllowed = minClearance - m_pcb->GetDesignSettings().GetDRCEpsilon();
int actual;
if( !checkClearancePadToPad( aRefPad, pad, clearanceAllowed, &actual ) )
@ -1378,7 +1376,7 @@ void DRC::setTransitions()
}
const int EPSILON = Mils2iu( 5 );
const int UI_EPSILON = Mils2iu( 5 );
wxPoint DRC::GetLocation( TRACK* aTrack, ZONE_CONTAINER* aConflictZone )
@ -1400,7 +1398,7 @@ wxPoint DRC::GetLocation( TRACK* aTrack, ZONE_CONTAINER* aConflictZone )
// Otherwise do a binary search for a "good enough" marker location
else
{
while( GetLineLength( pt1, pt2 ) > EPSILON )
while( GetLineLength( pt1, pt2 ) > UI_EPSILON )
{
if( conflictOutline->SquaredDistance( pt1 ) < conflictOutline->SquaredDistance( pt2 ) )
pt2 = ( pt1 + pt2 ) / 2;
@ -1408,7 +1406,7 @@ wxPoint DRC::GetLocation( TRACK* aTrack, ZONE_CONTAINER* aConflictZone )
pt1 = ( pt1 + pt2 ) / 2;
}
// Once we're within EPSILON pt1 and pt2 are "equivalent"
// Once we're within UI_EPSILON pt1 and pt2 are "equivalent"
return pt1;
}
}
@ -1420,7 +1418,7 @@ wxPoint DRC::GetLocation( TRACK* aTrack, const SEG& aConflictSeg )
wxPoint pt2 = aTrack->GetEnd();
// Do a binary search along the track for a "good enough" marker location
while( GetLineLength( pt1, pt2 ) > EPSILON )
while( GetLineLength( pt1, pt2 ) > UI_EPSILON )
{
if( aConflictSeg.SquaredDistance( pt1 ) < aConflictSeg.SquaredDistance( pt2 ) )
pt2 = ( pt1 + pt2 ) / 2;
@ -1428,7 +1426,7 @@ wxPoint DRC::GetLocation( TRACK* aTrack, const SEG& aConflictSeg )
pt1 = ( pt1 + pt2 ) / 2;
}
// Once we're within EPSILON pt1 and pt2 are "equivalent"
// Once we're within UI_EPSILON pt1 and pt2 are "equivalent"
return pt1;
}

7
pcbnew/drc/drc_clearance_test_functions.cpp
View File

@ -355,9 +355,6 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
/* Phase 1 : test DRC track to pads : */
/******************************************/
// Allow an epsilon at least as great as our allowed polygonisation error.
int epsilon = m_pcb->GetDesignSettings().m_MaxError;
// Compute the min distance to pads
for( MODULE* mod : m_pcb->Modules() )
{
@ -419,7 +416,7 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
SEG slotSeg( slotStart, slotEnd );
int widths = ( slotWidth + refSegWidth ) / 2;
int center2centerAllowed = minClearance + widths + epsilon;
int center2centerAllowed = minClearance + widths + bds.GetDRCEpsilon();
// Avoid square-roots if possible (for performance)
SEG::ecoord center2center_squared = refSeg.SquaredDistance( slotSeg );
@ -446,7 +443,7 @@ void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aS
}
int minClearance = aRefSeg->GetClearance( pad, &m_clearanceSource );
int clearanceAllowed = minClearance - epsilon;
int clearanceAllowed = minClearance - bds.GetDRCEpsilon();
int actual;
if( !checkClearanceSegmToPad( refSeg, refSegWidth, pad, clearanceAllowed, &actual ) )