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Sim QA: Add rlc project to test RLC ideal model inference

This commit is contained in:
Mikolaj Wielgus 2022-08-08 17:06:05 +02:00
parent 5096f5d8a9
commit f6771ed789
6 changed files with 5 additions and 1388 deletions
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20
qa/data/eeschema/spice_netlists/passives/passives.cir
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@ -1,20 +0,0 @@
.title KiCad schematic
.include "passives.lib"
.model __R2 r(
+ r=10Meg tnom=20 tc1=100u )
.model __C2 c(
+ c=100u tnom=15 tc1=21.4u )
.model __L2 l(
+ l=220n tnom=20 tc1=125u )
.save all
.probe alli
.dc TEMP -40 125 1
R2 VCC GND __R2
C2 VCC GND __C2
R1 VCC GND VISHAY_CRCW060310M0FKTABC
L1 VCC GND AVX_0603WL221GT
C1 VCC GND AVX_12066D107MAT4A
VDC1 VCC GND ( 1 )
L2 VCC GND __L2
.end

2
qa/data/eeschema/spice_netlists/passives/passives.kicad_pcb
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@ -1,2 +0,0 @@
(kicad_pcb (version 20220308) (generator pcbnew)
)

332
qa/data/eeschema/spice_netlists/passives/passives.kicad_pro
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@ -1,332 +0,0 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
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0,
1,
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0,
1,
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2,
2,
2,
2
],
[
0,
0,
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0,
1,
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],
[
0,
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0,
0,
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0,
1,
1,
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1,
1,
2
],
[
0,
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0,
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2
],
[
0,
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0,
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0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
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0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
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1,
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2,
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2,
2
],
[
0,
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0,
0,
2
],
[
0,
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2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "passives.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Spice",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"spice_save_all_currents": true,
"spice_save_all_voltages": true,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"24a3b022-7ece-4686-93db-0efadfbf9409",
""
]
],
"text_variables": {}
}

1020
qa/data/eeschema/spice_netlists/passives/passives.kicad_sch
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11
qa/data/eeschema/spice_netlists/passives/passives.lib
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@ -1,11 +0,0 @@
*
* Resistors
.model PT100 R(R=100 Tnom=0 tc1=3.85m noisy=0)
.model VISHAY_CRCW060310M0FKTABC R(R=10Meg Tnom=20 tc1=100u) ; bv_max=75 - idk if we should include that
* Capacitors
.model AVX_12066D107MAT4A C(C=100u Tnom=15 tc1=21.4u)
* Inductors
.model AVX_0603WL221GT L(ind=220n Tnom=20 tc1=125u)

8
qa/unittests/eeschema/test_netlist_exporter_spice.cpp
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@ -246,10 +246,12 @@ BOOST_AUTO_TEST_CASE( NpnCeAmp )
// Incomplete. TODO.
/*BOOST_AUTO_TEST_CASE( Passives )
BOOST_AUTO_TEST_CASE( Rlc )
{
TestNetlist( "passives" );
}*/
TestNetlist( "rlc" );
TestTranPoint( 9.43e-3, { { "V(/Vp)", -19e-3 }, { "I(Rs)", 19e-3 } } );
TestTranPoint( 9.74e-3, { { "V(/Vp)", 19e-3 }, { "I(Rs)", -19e-3 } } );
}
BOOST_AUTO_TEST_CASE( Tlines )