Add false-negative DRC tests (and fix first bug found by them).

This commit is contained in:
Jeff Young 2021-07-31 16:31:38 +01:00
parent 7b4dcb6e10
commit faa1ff4ec6
28 changed files with 65625 additions and 57 deletions

View File

@ -109,6 +109,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE*
drce->SetViolatingRule( constraint.GetParentRule() ); drce->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drce, (wxPoint) pos ); reportViolation( drce, (wxPoint) pos );
return false; // don't report violations with multiple edges; one is enough
} }
return true; return true;
@ -153,8 +154,8 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
if( shape->GetShape() == SHAPE_T::RECT ) if( shape->GetShape() == SHAPE_T::RECT )
{ {
// A single rectangle for the board would make the RTree useless, so // A single rectangle for the board would make the RTree useless, so convert
// convert to 4 edges // to 4 edges
edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) ); edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
edges.back()->SetShape( SHAPE_T::SEGMENT ); edges.back()->SetShape( SHAPE_T::SEGMENT );
edges.back()->SetEndX( shape->GetStartX() ); edges.back()->SetEndX( shape->GetStartX() );
@ -175,7 +176,8 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
} }
else if( shape->GetShape() == SHAPE_T::POLY ) else if( shape->GetShape() == SHAPE_T::POLY )
{ {
// Same for polygons // A single polygon for the board would make the RTree useless, so convert
// to n edges.
SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 ); SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii ) for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
@ -205,7 +207,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ), forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ),
queryBoardOutlineItems ); queryBoardOutlineItems );
forEachGeometryItem( s_allBasicItemsButZones, LSET::AllCuMask(), queryBoardGeometryItems ); forEachGeometryItem( s_allBasicItemsButZones, LSET::AllLayersMask(), queryBoardGeometryItems );
for( const std::unique_ptr<PCB_SHAPE>& edge : edges ) for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
{ {
@ -255,14 +257,21 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) ) if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) )
{ {
edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr, if( edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
[&]( BOARD_ITEM* edge ) -> bool [&]( BOARD_ITEM* edge ) -> bool
{ {
return testAgainstEdge( item, itemShape.get(), edge, return testAgainstEdge( item, itemShape.get(), edge,
SILK_CLEARANCE_CONSTRAINT, SILK_CLEARANCE_CONSTRAINT,
DRCE_SILK_MASK_CLEARANCE ); DRCE_SILK_MASK_CLEARANCE );
}, },
m_largestClearance ); m_largestClearance ) )
{
// violations reported during QueryColliding
}
else
{
// TODO: check postion being outside board boundary
}
} }
} }
} }

670
qa/data/issue1358.kicad_pcb Normal file
View File

@ -0,0 +1,670 @@
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400
qa/data/issue1358.kicad_pro Executable file
View File

@ -0,0 +1,400 @@
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293
qa/data/issue18.kicad_pcb Normal file
View File

@ -0,0 +1,293 @@
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184
qa/data/issue2528.kicad_pro Normal file
View File

@ -0,0 +1,184 @@
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View File

@ -84,7 +84,7 @@
"padstack": "error", "padstack": "error",
"pth_inside_courtyard": "ignore", "pth_inside_courtyard": "ignore",
"shorting_items": "error", "shorting_items": "error",
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"silk_overlap": "error", "silk_overlap": "error",
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"too_many_vias": "error", "too_many_vias": "error",

445
qa/data/issue5313.kicad_pcb Executable file
View File

@ -0,0 +1,445 @@
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460
qa/data/issue5750.kicad_pcb Normal file
View File

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155
qa/data/issue5854.kicad_pcb Normal file
View File

@ -0,0 +1,155 @@
(kicad_pcb (version 20210722) (generator pcbnew)
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486
qa/data/issue5854.kicad_pro Normal file
View File

@ -0,0 +1,486 @@
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[
"00000000-0000-0000-0000-00005d84b44c",
"I2C-interface"
]
],
"text_variables": {}
}

View File

@ -57,7 +57,7 @@
], ],
"drc_exclusions": [], "drc_exclusions": [],
"meta": { "meta": {
"version": 1 "version": 2
}, },
"rule_severities": { "rule_severities": {
"annular_width": "error", "annular_width": "error",
@ -85,7 +85,7 @@
"padstack": "error", "padstack": "error",
"pth_inside_courtyard": "ignore", "pth_inside_courtyard": "ignore",
"shorting_items": "error", "shorting_items": "error",
"silk_over_copper": "error", "silk_over_copper": "ignore",
"silk_overlap": "error", "silk_overlap": "error",
"skew_out_of_range": "error", "skew_out_of_range": "error",
"too_many_vias": "error", "too_many_vias": "error",

16
qa/data/issue6879.kicad_dru Executable file
View File

@ -0,0 +1,16 @@
(version 1)
(rule "PTH to Track Clearance"
(constraint hole_clearance (min 1.0mm))
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && B.Type =='Track'")
)
(rule "NPTH to Track Clearance"
(constraint hole_clearance (min 1.0mm))
(condition "(A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical') && B.Type =='Track'")
)
(rule "Max Drill Hole Size Mechanical"
(constraint hole (max 2.0mm))
(condition "A.Type == 'Pad'")
)

508
qa/data/issue6879.kicad_pcb Executable file
View File

@ -0,0 +1,508 @@
(kicad_pcb (version 20201220) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "Net-(C1-Pad2)")
(net 2 "Net-(C1-Pad1)")
(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad" (layer "F.Cu")
(tedit 56D1B4CB) (tstamp 7a5e0185-cb99-4816-a212-1cb5fdda6fe8)
(at 186.25 88.75)
(descr "Mounting Hole 3.2mm, M3, DIN965")
(tags "mounting hole 3.2mm m3 din965")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/fb2e017d-a5c5-49fb-ba95-cb396aae3918")
(attr exclude_from_pos_files)
(fp_text reference "H3" (at 0 4) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 600b29e3-3ea7-48fd-a954-b81d7d21815f)
)
(fp_text value "PTH-3mm" (at 0 3.8) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 982881b5-77b1-4780-b97a-b48fc7c793a6)
)
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 1710c190-e24b-4590-9dd6-c08f5a3e6148)
)
(fp_circle (center 0 0) (end 2.8 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp 533cb978-4c67-4904-86ed-173bc2ff1b45))
(fp_circle (center 0 0) (end 3.05 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp c08b7dbb-612b-43e9-a6cc-d4e66c1ea404))
(pad "1" thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask) (tstamp cfbc907d-8a25-46e9-a224-6b8152fa214f))
)
(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad" (layer "F.Cu")
(tedit 56D1B4CB) (tstamp 7effd7e7-a352-4b60-90dc-d04da9924f3e)
(at 166.25 88.75)
(descr "Mounting Hole 3.2mm, M3, DIN965")
(tags "mounting hole 3.2mm m3 din965")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/01326b80-c3a1-4c72-b881-eee45cdb68c5")
(attr exclude_from_pos_files)
(fp_text reference "H4" (at 0 4) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 3dfd39dc-326f-4ebf-a42f-a5544836a15a)
)
(fp_text value "PTH-3mm" (at 0 3.8) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp bbec47e3-9ffa-4d68-9bd8-d2c50951193f)
)
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp ba466aa3-f900-4724-b154-de8778c10cec)
)
(fp_circle (center 0 0) (end 2.8 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp 7f8e2e3b-3a66-47a9-a58a-28516317d286))
(fp_circle (center 0 0) (end 3.05 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp ee76c024-e387-4561-9d80-268c0015a52b))
(pad "1" thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask) (tstamp b5c3eb60-d01c-403e-abf7-cd1ddd2c14be))
)
(footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu")
(tedit 56D1B4CB) (tstamp b155e8e6-593a-4fdd-b7be-b9cbbe47b854)
(at 166.25 111)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/9c1f6247-3f70-4646-bb3c-a8c45bbfc056")
(attr exclude_from_pos_files)
(fp_text reference "H2" (at 0 -4.2) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp ccc0899b-bbf2-4044-9984-8b8b6c30c83f)
)
(fp_text value "NPTH-3mm" (at 0 4.2) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp b473fa3b-3b92-4646-b990-3a686d714123)
)
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp d71db0be-3896-4a51-beac-40768d8d3ef1)
)
(fp_circle (center 0 0) (end 3.2 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp d4901f12-4dae-4cd4-9bb1-5d962ba4e57d))
(fp_circle (center 0 0) (end 3.45 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 3d371e65-4ed5-435b-8cfc-b2bca6d607db))
(pad "1" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask) (tstamp 30bed439-ee98-4fbc-9d75-6c7a47f1e483))
)
(footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu")
(tedit 56D1B4CB) (tstamp dd6e559d-f8e5-4209-a83a-cd7404d50c5d)
(at 186.25 111)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/e0c75322-6681-4b92-9d80-a5c2e61fb79f")
(attr exclude_from_pos_files)
(fp_text reference "H1" (at 0 -4.2) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5b6ed842-a876-4bd0-8f81-70bdfe998dc6)
)
(fp_text value "NPTH-3mm" (at 0 4.2) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp fa284b56-4b5e-4ac6-bcab-b929f46c97c6)
)
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5054f0ca-f585-4ee1-a91e-658ca5387bf2)
)
(fp_circle (center 0 0) (end 3.2 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp ad1a6974-bb9c-4845-bf1b-4eb349a7b5f9))
(fp_circle (center 0 0) (end 3.45 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 7495fc84-6ec6-45ca-9071-d10637312859))
(pad "1" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask) (tstamp 3c6562ef-6330-45e0-b952-0a82c3116b50))
)
(footprint "Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical" (layer "F.Cu")
(tedit 5C28146C) (tstamp e918d824-8add-477a-bc72-c18e218465c7)
(at 165.5 101.25 90)
(descr "JST XH series connector, B2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator")
(tags "connector JST XH vertical")
(property "LCSC N°" "C20079")
(property "N°" "XH-2A")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/73dee3db-4043-47b4-b8c7-6ed59b861244")
(attr through_hole)
(fp_text reference "J1" (at -3.75 -2 180) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp f9009f25-1208-4105-9f60-1e769861c0b9)
)
(fp_text value "XH-2A" (at 1.25 4.6 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5addb007-8ec3-4029-b4b3-109887a8afbf)
)
(fp_text user "${REFERENCE}" (at 1.25 2.7 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp aa56998b-ed2f-428f-b788-3cb40902350a)
)
(fp_line (start 1.75 -1.7) (end 1.75 -2.45) (layer "F.SilkS") (width 0.12) (tstamp 0adc786e-c434-4492-a65f-ea2dbf023bbb))
(fp_line (start 3.25 -2.45) (end 3.25 -1.7) (layer "F.SilkS") (width 0.12) (tstamp 0d7ef226-df0e-4ed6-9909-f4b0f354bab3))
(fp_line (start -0.75 -1.7) (end -0.75 -2.45) (layer "F.SilkS") (width 0.12) (tstamp 160e3aa7-3701-49c7-ad98-92f1e15d11f8))
(fp_line (start -0.75 -2.45) (end -2.55 -2.45) (layer "F.SilkS") (width 0.12) (tstamp 2b7bbe5f-c126-44cb-b4b1-e244ebde95ee))
(fp_line (start 5.06 3.51) (end 5.06 -2.46) (layer "F.SilkS") (width 0.12) (tstamp 3a2be3ae-5b9f-4985-b114-a1d73118bdd5))
(fp_line (start 4.3 2.75) (end 1.25 2.75) (layer "F.SilkS") (width 0.12) (tstamp 4e612ece-fe1a-4dc9-bcaa-56144fb56ae7))
(fp_line (start 1.75 -2.45) (end 0.75 -2.45) (layer "F.SilkS") (width 0.12) (tstamp 693f5d3d-c257-4591-ba57-643f4dd8f12f))
(fp_line (start -1.8 2.75) (end 1.25 2.75) (layer "F.SilkS") (width 0.12) (tstamp 72ff50c9-cd49-4a9d-95e2-0bddea9e2ec6))
(fp_line (start -2.85 -2.75) (end -2.85 -1.5) (layer "F.SilkS") (width 0.12) (tstamp 8b531cb0-7ec5-4668-88c3-ed1f751d9ae0))
(fp_line (start -2.56 3.51) (end 5.06 3.51) (layer "F.SilkS") (width 0.12) (tstamp 8db24d26-d584-4a2b-b885-53f2a17f7f23))
(fp_line (start 5.05 -0.2) (end 4.3 -0.2) (layer "F.SilkS") (width 0.12) (tstamp 9ad31be3-f81c-4b40-93c6-8b9855b7b1e8))
(fp_line (start 5.05 -1.7) (end 5.05 -2.45) (layer "F.SilkS") (width 0.12) (tstamp a2f9f4d8-e32c-4580-80ed-c6cc2fa36113))
(fp_line (start 0.75 -2.45) (end 0.75 -1.7) (layer "F.SilkS") (width 0.12) (tstamp aac2db70-65e0-4898-bd39-c8b4fba038bd))
(fp_line (start -2.55 -0.2) (end -1.8 -0.2) (layer "F.SilkS") (width 0.12) (tstamp aef9a042-b20f-4834-b164-e4cc1cb1f32b))
(fp_line (start -1.6 -2.75) (end -2.85 -2.75) (layer "F.SilkS") (width 0.12) (tstamp b5f184ae-0e27-4509-8a1d-e7b96ae4c9fa))
(fp_line (start 4.3 -0.2) (end 4.3 2.75) (layer "F.SilkS") (width 0.12) (tstamp cc8b3c58-18e6-4da7-a2a3-9ecde619a75c))
(fp_line (start -2.56 -2.46) (end -2.56 3.51) (layer "F.SilkS") (width 0.12) (tstamp d1320845-83f4-4737-b44b-07cd86704024))
(fp_line (start 3.25 -1.7) (end 5.05 -1.7) (layer "F.SilkS") (width 0.12) (tstamp d7823cab-9c8f-4dc0-9506-0a2a7b8fdae4))
(fp_line (start 5.05 -2.45) (end 3.25 -2.45) (layer "F.SilkS") (width 0.12) (tstamp dc90412b-136f-45a5-a31f-0b39e3721120))
(fp_line (start 5.06 -2.46) (end -2.56 -2.46) (layer "F.SilkS") (width 0.12) (tstamp e9fcc632-df34-4d57-8ec2-22abfbb30b49))
(fp_line (start 0.75 -1.7) (end 1.75 -1.7) (layer "F.SilkS") (width 0.12) (tstamp ed07a464-ed7a-413f-8d50-8d9c57b9309e))
(fp_line (start -2.55 -2.45) (end -2.55 -1.7) (layer "F.SilkS") (width 0.12) (tstamp f242d7ed-dd2b-4b02-8b66-0400b2ebf1ca))
(fp_line (start -2.55 -1.7) (end -0.75 -1.7) (layer "F.SilkS") (width 0.12) (tstamp f63d17db-7403-4945-9e25-4449fa42e5d6))
(fp_line (start -1.8 -0.2) (end -1.8 2.75) (layer "F.SilkS") (width 0.12) (tstamp fd2a834b-e8e8-4a59-91b4-ad4e82a6491f))
(fp_line (start -2.95 3.9) (end 5.45 3.9) (layer "F.CrtYd") (width 0.05) (tstamp 4474e8cf-5c61-44f1-8ff7-1135bc46ae95))
(fp_line (start -2.95 -2.85) (end -2.95 3.9) (layer "F.CrtYd") (width 0.05) (tstamp 8b55d4c2-87a8-403f-838c-e6b39d114ff0))
(fp_line (start 5.45 -2.85) (end -2.95 -2.85) (layer "F.CrtYd") (width 0.05) (tstamp e1ec3d4c-ab08-4d7a-8324-c084d2f73cc2))
(fp_line (start 5.45 3.9) (end 5.45 -2.85) (layer "F.CrtYd") (width 0.05) (tstamp feda8083-3526-4fc0-8620-a5e5ff75c5c7))
(fp_line (start 0 -1.35) (end 0.625 -2.35) (layer "F.Fab") (width 0.1) (tstamp 049059f8-ba6f-4aa3-bf0e-92fba6efdda8))
(fp_line (start -2.45 -2.35) (end -2.45 3.4) (layer "F.Fab") (width 0.1) (tstamp 2b5a54ae-a37d-4aff-a271-0f825a8e855d))
(fp_line (start 4.95 -2.35) (end -2.45 -2.35) (layer "F.Fab") (width 0.1) (tstamp 757b9ed4-8089-4438-80e3-665859bf0e00))
(fp_line (start -2.45 3.4) (end 4.95 3.4) (layer "F.Fab") (width 0.1) (tstamp b6e260db-b404-43d2-9d13-3d72bf702940))
(fp_line (start -0.625 -2.35) (end 0 -1.35) (layer "F.Fab") (width 0.1) (tstamp d901e84b-f741-4b4a-93a0-440497371c23))
(fp_line (start 4.95 3.4) (end 4.95 -2.35) (layer "F.Fab") (width 0.1) (tstamp e9b8a997-2bef-41da-8437-468ed47a22a5))
(pad "1" thru_hole roundrect (at 0 0 90) (size 1.7 2) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.147059)
(net 2 "Net-(C1-Pad1)") (pinfunction "Pin_1") (tstamp 3bbb4641-3942-4c40-a8f5-028930bd1924))
(pad "2" thru_hole oval (at 2.5 0 90) (size 1.7 2) (drill 1) (layers *.Cu *.Mask)
(net 1 "Net-(C1-Pad2)") (pinfunction "Pin_2") (tstamp 63fbe990-c88a-466e-a812-693fc90734fb))
(model "${KISYS3DMOD}/Connector_JST.3dshapes/JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" (layer "F.Cu")
(tedit 5AE50EF1) (tstamp fecac377-cfa5-4d67-9270-d63a7c66c00c)
(at 180 102.25 90)
(descr "CP, Radial series, Radial, pin pitch=5.00mm, , diameter=10mm, Electrolytic Capacitor")
(tags "CP Radial series Radial pin pitch 5.00mm diameter 10mm Electrolytic Capacitor")
(property "LCSC N°" "C269977")
(property "N°" "NPXE21E102MF")
(property "Sheet file" "Test.kicad_sch")
(property "Sheet name" "")
(path "/7ebeac02-393a-4151-9559-9db3b8be9961")
(attr through_hole)
(fp_text reference "C1" (at -3.75 0 180) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp e5e52899-e0de-4e04-8746-78b577c36af5)
)
(fp_text value "1m25vPY_5x10x16" (at 2.5 6.25 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 98f8be92-7c06-4a54-97f1-61787cc482c3)
)
(fp_text user "${REFERENCE}" (at 2.5 0 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 79624cc3-c938-4ff0-8a1f-3b13ce2aa3d3)
)
(fp_line (start 7.501 -1.062) (end 7.501 1.062) (layer "F.SilkS") (width 0.12) (tstamp 00b05f18-0e06-4b46-821b-c7f161938bac))
(fp_line (start 4.181 -4.797) (end 4.181 -1.241) (layer "F.SilkS") (width 0.12) (tstamp 01f2e100-cdd3-42bd-acf5-7a88e45cce89))
(fp_line (start 5.501 1.241) (end 5.501 4.11) (layer "F.SilkS") (width 0.12) (tstamp 024a7aca-bec2-4578-8445-48a708a13045))
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394
qa/data/issue6879.kicad_pro Executable file
View File

@ -0,0 +1,394 @@
{
"board": {
"design_settings": {
"defaults": {
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"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
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"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
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"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_too_small": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_too_small": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
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"allow_microvias": false,
"max_error": 0.005,
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"min_hole_clearance": 0.0,
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"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.6,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
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],
"via_dimensions": [
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}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
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0,
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0,
2,
2,
2,
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],
[
0,
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0,
0,
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],
[
0,
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0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "Test.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"8f39686c-273b-419b-9330-c9f7a9a20c4d",
""
]
],
"text_variables": {}
}

61
qa/data/issue6945.kicad_dru Executable file
View File

@ -0,0 +1,61 @@
(version 1)
(rule "Distance between 1mm test points"
(constraint courtyard_clearance (min 1.54mm))
(condition "A.Reference =='TP*' && B.Reference == 'TP*")
)
(rule "Distance between Vias Hole Same Nets"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type =='Via' && B.Type =='Via' && A.Net == B.Net")
)
(rule "Distance between Vias Hole Different Nets"
(constraint hole_to_hole (min 0.5mm))
(condition "A.Type =='Via' && B.Type =='Via' && A.Net != B.Net")
)
(rule "Via Hole to Track Clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type =='Via' && B.Type =='Track'")
)
(rule "Pad to Track Clearance"
(constraint clearance (min 0.2mm))
(condition "A.Type =='Pad' && B.Type =='Track'")
)
(rule "Distance between Pads Hole Same Nets"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type =='Pad' && B.Type =='Pad' && A.Net == B.Net")
)
(rule "Distance between Pads Hole Different Nets"
(constraint hole_to_hole (min 0.50mm))
(condition "A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net")
)
(rule "PTH to Track Clearance"
(constraint hole_clearance (min 0.33mm))
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && B.Type =='Track'")
)
(rule "NPTH to Track Clearance"
(constraint hole_clearance (min 0.254mm))
(condition "(A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical') && B.Type =='Track'")
)
(rule "Max Drill Hole Size Mechanical"
(constraint hole (max 6.3mm))
(condition "A.Pad_Type == 'NPTH, mechanical'")
)
(rule "Max Drill Hole Size PTH"
(constraint hole (max 6.35mm))
(condition "A.Pad_Type == 'Through-hole'")
)
#TEST
(rule "Disallow via in testpoint pad"
(constraint disallow via)
(condition "A.insideCourtyard('TP*')")
)

1387
qa/data/issue6945.kicad_pcb Executable file

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,84 @@
(kicad_pcb (version 20210722) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(gr_rect (start 78.105 50.165) (end 228.6 130.81) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp d0d883cf-992c-40b1-8baf-44f8b31bd338))
(gr_text "Text should generate DRC warning...." (at 202.565 119.38) (layer "Edge.Cuts") (tstamp dc3e6522-5d53-4f8e-b319-7cf9c7db49ec)
(effects (font (size 1 1) (thickness 0.15)))
)
)

149
qa/data/issue7267.kicad_pcb Normal file
View File

@ -0,0 +1,149 @@
(kicad_pcb (version 20210722) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "signal")
(footprint "Housings_DIP:DIP-14_W7.62mm_LongPads" (layer "F.Cu")
(tedit 6105426B) (tstamp 3bd3a1e0-b35d-4974-99fa-33d3eee5d601)
(at 154.305 74.93)
(descr "14-lead dip package, row spacing 7.62 mm (300 mils), longer pads")
(tags "dil dip 2.54 300")
(attr through_hole)
(fp_text reference "REF**" (at 0 -5.22) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 59609e9e-6f8e-414a-8e1a-68271157d0f4)
)
(fp_text value "DIP-14_W7.62mm_LongPads" (at 0 -3.72) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 777520c7-f251-417a-a971-c4b28beed159)
)
(fp_line (start 0.135 17.535) (end 0.135 16.265) (layer "F.SilkS") (width 0.15) (tstamp 0b79ddb5-29b5-4d02-b254-210c2c0bc52a))
(fp_line (start 0.135 17.535) (end 7.485 17.535) (layer "F.SilkS") (width 0.15) (tstamp 0f83140d-7d8e-4df7-9004-7d55d208e970))
(fp_line (start 7.485 -2.295) (end 7.485 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 47d1c952-cc7e-48d8-8bf3-43e84030b5b6))
(fp_line (start 7.485 17.535) (end 7.485 16.265) (layer "F.SilkS") (width 0.15) (tstamp 4a6fe592-662f-4920-ac12-4fe3becc67da))
(fp_line (start 0.135 -1.025) (end -1.15 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 4c82108f-9f12-4804-907e-f81706f9251d))
(fp_line (start 0.135 -2.295) (end 7.485 -2.295) (layer "F.SilkS") (width 0.15) (tstamp e79a53c0-2b0d-4f45-9b3a-0d8f6a3f73f2))
(fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer "F.SilkS") (width 0.15) (tstamp fddf502b-35d9-4c79-83ea-e86b1347b469))
(fp_rect (start 2.286 0.127) (end 5.334 14.732) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp 1d78c688-c2db-4868-a03f-0436a459cbaf))
(fp_line (start 9 -2.45) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 2fe33ec7-1451-4a28-bf38-24c176dee936))
(fp_line (start -1.4 -2.45) (end -1.4 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 9873122d-04aa-4cf6-96df-5df12ef3440f))
(fp_line (start -1.4 -2.45) (end 9 -2.45) (layer "F.CrtYd") (width 0.05) (tstamp 9abef0ec-7068-4aa5-a4b2-c8cd8b0ceb6e))
(fp_line (start -1.4 17.7) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp c1c9a072-3005-4d0b-b7f6-70565ddfb731))
(pad "1" thru_hole oval locked (at 0 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 2fe6f3ef-3519-45f5-bd91-8d7847304292))
(pad "2" thru_hole oval locked (at 0 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 4f8caf82-f2fe-4ebb-b03c-0226aa886a96))
(pad "3" thru_hole oval locked (at 0 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp a01719d5-72b8-433b-882b-36b730f1b10d))
(pad "4" thru_hole oval locked (at 0 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "signal") (tstamp 7616ae07-fea3-41ec-baf7-0f401270819a))
(pad "5" thru_hole oval locked (at 0 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3443dd40-4950-45cf-ab02-9e2253c6bb3c))
(pad "6" thru_hole oval locked (at 0 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp cf6b8e1e-93f3-4e63-9f77-8c9ec064201c))
(pad "7" thru_hole oval locked (at 0 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp f522aabe-6821-4dcd-853d-a284f451356d))
(pad "8" thru_hole oval locked (at 7.62 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp db0b3374-d270-4249-87b7-9a0a6163297e))
(pad "9" thru_hole oval locked (at 7.62 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 07dd9b8f-a4b6-4b90-9868-4559ed6f6a32))
(pad "10" thru_hole oval locked (at 7.62 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 036d5919-6a4b-49ac-851e-0b99804de700))
(pad "11" thru_hole oval locked (at 7.62 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 54ecef87-4bce-44eb-93cf-a1f86ce2bb62))
(pad "12" thru_hole oval locked (at 7.62 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "signal") (tstamp 2f3483f5-a99f-4f68-b6b1-fe893d5ab874))
(pad "13" thru_hole oval locked (at 7.62 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 30760006-239e-48b2-9ad2-bdc85ca119ed))
(pad "14" thru_hole oval locked (at 7.62 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp fefb1ddf-3d2b-4862-9521-565bc091912b))
(model "Housings_DIP.3dshapes/DIP-14_W7.62mm_LongPads.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(gr_rect (start 78.105 50.165) (end 228.6 130.81) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp d0d883cf-992c-40b1-8baf-44f8b31bd338))
(segment (start 159.385 80.01) (end 156.845 82.55) (width 0.25) (layer "F.Cu") (net 1) (tstamp 21b5daa4-e65f-4e1c-a333-2091740a1e4a))
(segment (start 156.845 82.55) (end 154.305 82.55) (width 0.25) (layer "F.Cu") (net 1) (tstamp 3d3d3243-6bbc-49ec-beed-2a25912450f2))
(segment (start 161.925 80.01) (end 238.125 80.01) (width 0.25) (layer "F.Cu") (net 1) (tstamp 621611c9-2b28-46fa-ba36-db611bc29586))
(segment (start 161.925 80.01) (end 159.385 80.01) (width 0.25) (layer "F.Cu") (net 1) (tstamp d3322cbe-61d2-451b-b61a-efdb757a7742))
)

427
qa/data/issue7267.kicad_pro Executable file
View File

@ -0,0 +1,427 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.0,
"copper_text_size_v": 1.0,
"copper_text_thickness": 0.19999999999999998,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 1,
"dimension_units": 2,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 1,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 0.8128,
"fab_text_size_v": 0.8128,
"fab_text_thickness": 0.15239999999999998,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 0.8128,
"other_text_size_v": 0.8128,
"other_text_thickness": 0.15239999999999998,
"other_text_upright": false,
"pads": {
"drill": 3.2,
"height": 6.0,
"width": 6.0
},
"silk_line_width": 0.15239999999999998,
"silk_text_italic": false,
"silk_text_size_h": 0.8128,
"silk_text_size_v": 0.8128,
"silk_text_thickness": 0.15239999999999998,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.2032
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "ignore",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.2032,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.15,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.2032,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.6,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
0.0,
0.2032,
0.254,
0.3048,
0.4064,
0.508,
0.6096,
0.8128,
1.016,
1.27,
1.524,
1.778,
2.032,
2.286,
2.54
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.7,
"drill": 0.4
},
{
"diameter": 0.8,
"drill": 0.5
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "020.02.010.0221.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2032,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2032,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 36.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
"AM2315 sensors I2C interface"
],
[
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
"230V & general interface"
],
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
""
]
],
"text_variables": {}
}

7
qa/data/issue7325.kicad_dru Executable file
View File

@ -0,0 +1,7 @@
#(version 1.0)
#(rule silk2via
# (constraint silk_clearance(min 0.15mm))
# (condition "A.Type=='*Text' && B.Type=='Via'"))
#(rule silk2via1
#(constraint silk_clearance(min 0.15mm))
#(condition "A.Type=='Graphic*' && B.Type=='Via'"))

57761
qa/data/issue7325.kicad_pcb Executable file

File diff suppressed because it is too large Load Diff

427
qa/data/issue7325.kicad_pro Executable file
View File

@ -0,0 +1,427 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.0,
"copper_text_size_v": 1.0,
"copper_text_thickness": 0.19999999999999998,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 1,
"dimension_units": 2,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 1,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 0.8128,
"fab_text_size_v": 0.8128,
"fab_text_thickness": 0.15239999999999998,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 0.8128,
"other_text_size_v": 0.8128,
"other_text_thickness": 0.15239999999999998,
"other_text_upright": false,
"pads": {
"drill": 3.2,
"height": 6.0,
"width": 6.0
},
"silk_line_width": 0.15239999999999998,
"silk_text_italic": false,
"silk_text_size_h": 0.8128,
"silk_text_size_v": 0.8128,
"silk_text_thickness": 0.15239999999999998,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.2032
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.2032,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.0,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.15,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.2032,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.6,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": -0.0
},
"track_widths": [
0.0,
0.2032,
0.254,
0.3048,
0.4064,
0.508,
0.6096,
0.8128,
1.016,
1.27,
1.524,
1.778,
2.032,
2.286,
2.54
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.7,
"drill": 0.4
},
{
"diameter": 0.8,
"drill": 0.5
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "020.02.010.0221.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2032,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2032,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 36.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
"AM2315 sensors I2C interface"
],
[
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
"230V & general interface"
],
[
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
""
]
],
"text_variables": {}
}

View File

@ -0,0 +1,9 @@
(version 1)
(rule "keepout holes"
(constraint disallow hole)
(condition "A.insideArea('NoBottomFootprints')" )
)
(rule "keepout bottom footprints"
(constraint disallow pad)
(condition "A.Layer_Bottom && A.insideArea('NoBottomFootprints')" )
)

343
qa/data/issue7567.kicad_pcb Normal file
View File

@ -0,0 +1,343 @@
(kicad_pcb (version 20210126) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(aux_axis_origin 96.52 144.78)
(grid_origin 96.52 144.78)
(pcbplotparams
(layerselection 0x00000fc_80000001)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "GND")
(net 2 "+5V")
(net 3 "+3V3")
(net 4 "GPIO_SPI_CS#")
(net 5 "GPIO_UART1_TXD")
(net 6 "GPIO_SPI_MISO")
(net 7 "GPIO_UART1_RXD")
(net 8 "GPIO_SPI_MOSI")
(net 9 "GPIO_UART1_CTS")
(net 10 "GPIO_SPI_CLK")
(net 11 "GPIO_UART1_RTS")
(net 12 "GPIO_I2C_SCL")
(net 13 "GPIO_I2S_CLK")
(net 14 "GPIO_I2C_SDA")
(net 15 "GPIO_I2S_FRM")
(net 16 "GPIO_UART2_TXD")
(net 17 "GPIO_I2S_DO")
(net 18 "GPIO_UART2_RXD")
(net 19 "GPIO_I2S_DI")
(net 20 "GPIO_S5_0")
(net 21 "GPIO_PWM0")
(net 22 "GPIO_S5_1")
(net 23 "GPIO_PWM1")
(net 24 "GPIO_S5_2")
(net 25 "I2SMCLK_GPIO")
(footprint "Pin_Headers:Pin_Header_Straight_2x13" locked (layer "F.Cu")
(tedit 577F1E14) (tstamp 00000000-0000-0000-0000-000057710c62)
(at 109.855 142.24 90)
(descr "Through hole pin header")
(tags "pin header")
(path "/00000000-0000-0000-0000-0000576c994f")
(attr through_hole)
(fp_text reference "P1" (at 1.27 -3.175 90) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp df6ea7ea-4c97-406e-b3d5-74ea4b56d842)
)
(fp_text value "CONN_02X13" (at 5.08 3.175 180) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 0521fa67-7953-4a88-8d72-df0659d06791)
)
(fp_line (start 3.81 31.75) (end -1.27 31.75) (layer "F.SilkS") (width 0.15) (tstamp 30162e69-e978-4092-8abd-fb8cf99fe5ab))
(fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer "F.SilkS") (width 0.15) (tstamp 3167fff6-db1d-4c63-8d24-a011d71fcd96))
(fp_line (start -1.27 1.27) (end -1.27 31.75) (layer "F.SilkS") (width 0.15) (tstamp 4ec22dd7-3cbb-4efa-95a5-9b85d3a13668))
(fp_line (start -1.55 -1.55) (end -1.55 0) (layer "F.SilkS") (width 0.15) (tstamp 520abb36-f693-4622-b926-5fd5e9d9c40f))
(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer "F.SilkS") (width 0.15) (tstamp 76480a74-d043-445b-9be1-34656ab0d843))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer "F.SilkS") (width 0.15) (tstamp 8ca8e6ad-651f-477d-a59c-8edaf8b2b42c))
(fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer "F.SilkS") (width 0.15) (tstamp dbee2a3c-b78c-4689-9dd1-8914940b4295))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer "F.SilkS") (width 0.15) (tstamp fe0079fa-49e6-44bd-858a-d6eca245c70a))
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176
qa/data/issue8003.kicad_pcb Executable file
View File

@ -0,0 +1,176 @@
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View File

@ -56,21 +56,25 @@ struct DRC_REGRESSION_TEST_FIXTURE
} }
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString(); std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
std::string projectPath = absPath + ".kicad_pro"; wxFileName projectFile( absPath + ".kicad_pro" );
std::string boardPath = absPath + ".kicad_pcb"; std::string boardPath = absPath + ".kicad_pcb";
wxFileName rulesFile( absPath + ".kicad_dru" );
wxFileName pro( projectPath ); if( projectFile.Exists() )
m_settingsManager.LoadProject( projectFile.GetFullPath() );
if( pro.Exists() )
m_settingsManager.LoadProject( pro.GetFullPath() );
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath ); m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
if( pro.Exists() ) if( projectFile.Exists() )
m_board->SetProject( &m_settingsManager.Prj() ); m_board->SetProject( &m_settingsManager.Prj() );
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() ); m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
m_DRCEngine->InitEngine( wxFileName() );
if( rulesFile.Exists() )
m_DRCEngine->InitEngine( rulesFile );
else
m_DRCEngine->InitEngine( wxFileName() );
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine; m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
m_toolMgr = std::make_unique<TOOL_MANAGER>(); m_toolMgr = std::make_unique<TOOL_MANAGER>();
@ -105,15 +109,20 @@ BOOST_FIXTURE_TEST_SUITE( TestDRCRegressions, DRC_REGRESSION_TEST_FIXTURE )
constexpr int delta = KiROUND( 0.006 * IU_PER_MM ); constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
BOOST_AUTO_TEST_CASE( DRCRegressions ) BOOST_AUTO_TEST_CASE( DRCFalsePositiveRegressions )
{ {
for( const wxString& relPath : { "issue4139", // These documents at one time flagged DRC errors that they shouldn't have.
"issue4774",
"issue5978", std::vector<wxString> tests = { "issue4139",
"issue5990", "issue4774",
"issue6443", "issue5978",
"issue7975", "issue5990",
"issue8407" } ) "issue6443",
"issue7567",
"issue7975",
"issue8407" };
for( const wxString& relPath : tests )
{ {
loadBoard( relPath ); loadBoard( relPath );
fillZones( 6 ); fillZones( 6 );
@ -121,8 +130,8 @@ BOOST_AUTO_TEST_CASE( DRCRegressions )
std::vector<DRC_ITEM> violations; std::vector<DRC_ITEM> violations;
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings(); BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_WARNING; bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_IGNORE;
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_WARNING; bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_IGNORE;
m_DRCEngine->SetViolationHandler( m_DRCEngine->SetViolationHandler(
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos ) [&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
@ -133,17 +142,76 @@ BOOST_AUTO_TEST_CASE( DRCRegressions )
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false ); m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, %s", if( violations.empty() )
relPath, {
violations.empty() ? "passed" : "failed" ) ); BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", relPath ) );
}
if( !violations.empty() ) else
{ {
std::map<KIID, EDA_ITEM*> itemMap; std::map<KIID, EDA_ITEM*> itemMap;
m_board->FillItemMap( itemMap ); m_board->FillItemMap( itemMap );
for( const DRC_ITEM& item : violations ) for( const DRC_ITEM& item : violations )
BOOST_ERROR( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) ); {
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
itemMap ) );
}
BOOST_ERROR( wxString::Format( "DRC regression: %s, failed", relPath ) );
}
}
}
BOOST_AUTO_TEST_CASE( DRCFalseNegativeRegressions )
{
// These documents at one time failed to catch DRC errors that they should have.
std::vector< std::pair<wxString, int> > tests = { { "issue1358", 2 },
{ "issue2528", 1 },
{ "issue5750", 4 },
{ "issue5854", 3 },
{ "issue6879", 6 },
{ "issue6945", 2 },
{ "issue7241", 1 },
{ "issue7267", 4 },
{ "issue7325", 21 },
{ "issue8003", 2 } };
for( const std::pair<wxString, int>& entry : tests )
{
loadBoard( entry.first );
fillZones( 6 );
std::vector<DRC_ITEM> violations;
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
m_DRCEngine->SetViolationHandler(
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
{
violations.push_back( *aItem );
} );
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
if( violations.size() == entry.second )
{
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
}
else
{
BOOST_CHECK_EQUAL( violations.size(), entry.second );
std::map<KIID, EDA_ITEM*> itemMap;
m_board->FillItemMap( itemMap );
for( const DRC_ITEM& item : violations )
{
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
itemMap ) );
}
BOOST_ERROR( wxString::Format( "DRC regression: %s, failed", entry.first ) );
} }
} }
} }

View File

@ -56,21 +56,25 @@ struct ZONE_FILL_TEST_FIXTURE
} }
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString(); std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
std::string projectPath = absPath + ".kicad_pro"; wxFileName projectFile( absPath + ".kicad_pro" );
std::string boardPath = absPath + ".kicad_pcb"; std::string boardPath = absPath + ".kicad_pcb";
wxFileName rulesFile( absPath + ".kicad_dru" );
wxFileName pro( projectPath ); if( projectFile.Exists() )
m_settingsManager.LoadProject( projectFile.GetFullPath() );
if( pro.Exists() )
m_settingsManager.LoadProject( pro.GetFullPath() );
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath ); m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
if( pro.Exists() ) if( projectFile.Exists() )
m_board->SetProject( &m_settingsManager.Prj() ); m_board->SetProject( &m_settingsManager.Prj() );
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() ); m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
m_DRCEngine->InitEngine( wxFileName() );
if( rulesFile.Exists() )
m_DRCEngine->InitEngine( rulesFile );
else
m_DRCEngine->InitEngine( wxFileName() );
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine; m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
m_toolMgr = std::make_unique<TOOL_MANAGER>(); m_toolMgr = std::make_unique<TOOL_MANAGER>();
@ -233,16 +237,20 @@ BOOST_AUTO_TEST_CASE( NotchedZones )
BOOST_AUTO_TEST_CASE( RegressionZoneFillTests ) BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
{ {
for( const wxString& relPath : { "issue2568", std::vector<wxString> tests = { "issue18",
"issue3812", "issue2568",
"issue5102", "issue3812",
"issue5320", "issue5102",
"issue5567", "issue5313",
"issue5830", "issue5320",
"issue6039", "issue5567",
"issue6260", "issue5830",
"issue6284", "issue6039",
"issue7086" } ) "issue6260",
"issue6284",
"issue7086" };
for( const wxString& relPath : tests )
{ {
loadBoard( relPath ); loadBoard( relPath );
@ -261,18 +269,26 @@ BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false ); m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d fill algo %s", if( violations.empty() )
relPath, {
fillVersion, BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d algo passed",
violations.empty() ? "passed" : "failed" ) ); relPath,
fillVersion ) );
if( !violations.empty() ) }
else
{ {
std::map<KIID, EDA_ITEM*> itemMap; std::map<KIID, EDA_ITEM*> itemMap;
m_board->FillItemMap( itemMap ); m_board->FillItemMap( itemMap );
for( const DRC_ITEM& v : violations ) for( const DRC_ITEM& item : violations )
BOOST_ERROR( v.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) ); {
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
itemMap ) );
}
BOOST_ERROR( wxString::Format( "Zone fill regression: %s, V%d algo failed",
relPath,
fillVersion ) );
} }
} }
} }