Add false-negative DRC tests (and fix first bug found by them).
This commit is contained in:
parent
7b4dcb6e10
commit
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@ -109,6 +109,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE*
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drce->SetViolatingRule( constraint.GetParentRule() );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, (wxPoint) pos );
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reportViolation( drce, (wxPoint) pos );
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return false; // don't report violations with multiple edges; one is enough
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}
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}
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return true;
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return true;
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@ -153,8 +154,8 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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if( shape->GetShape() == SHAPE_T::RECT )
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if( shape->GetShape() == SHAPE_T::RECT )
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{
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{
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// A single rectangle for the board would make the RTree useless, so
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// A single rectangle for the board would make the RTree useless, so convert
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// convert to 4 edges
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// to 4 edges
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetEndX( shape->GetStartX() );
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edges.back()->SetEndX( shape->GetStartX() );
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@ -175,7 +176,8 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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}
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}
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else if( shape->GetShape() == SHAPE_T::POLY )
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else if( shape->GetShape() == SHAPE_T::POLY )
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{
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{
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// Same for polygons
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// A single polygon for the board would make the RTree useless, so convert
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// to n edges.
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SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
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SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
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for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
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for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
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@ -205,7 +207,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ),
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forEachGeometryItem( { PCB_SHAPE_T, PCB_FP_SHAPE_T }, LSET( 2, Edge_Cuts, Margin ),
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queryBoardOutlineItems );
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queryBoardOutlineItems );
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forEachGeometryItem( s_allBasicItemsButZones, LSET::AllCuMask(), queryBoardGeometryItems );
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forEachGeometryItem( s_allBasicItemsButZones, LSET::AllLayersMask(), queryBoardGeometryItems );
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for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
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for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
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{
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{
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@ -255,14 +257,21 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) )
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if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) )
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{
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{
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edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
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if( edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
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[&]( BOARD_ITEM* edge ) -> bool
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[&]( BOARD_ITEM* edge ) -> bool
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{
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{
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return testAgainstEdge( item, itemShape.get(), edge,
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return testAgainstEdge( item, itemShape.get(), edge,
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SILK_CLEARANCE_CONSTRAINT,
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SILK_CLEARANCE_CONSTRAINT,
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DRCE_SILK_MASK_CLEARANCE );
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DRCE_SILK_MASK_CLEARANCE );
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},
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},
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m_largestClearance );
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m_largestClearance ) )
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{
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// violations reported during QueryColliding
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}
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else
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{
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// TODO: check postion being outside board boundary
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}
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}
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}
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}
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}
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}
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}
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@ -0,0 +1,670 @@
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(kicad_pcb (version 20210722) (generator pcbnew)
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(general
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(thickness 1.6)
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)
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(paper "A4")
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(layers
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(0 "F.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user "B.Adhesive")
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(33 "F.Adhes" user "F.Adhesive")
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user "B.Silkscreen")
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(37 "F.SilkS" user "F.Silkscreen")
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user "User.Drawings")
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(41 "Cmts.User" user "User.Comments")
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(42 "Eco1.User" user "User.Eco1")
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(43 "Eco2.User" user "User.Eco2")
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user "B.Courtyard")
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(47 "F.CrtYd" user "F.Courtyard")
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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)
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(setup
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(pad_to_mask_clearance 0.051)
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(solder_mask_min_width 0.25)
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(pcbplotparams
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(layerselection 0x00010fc_ffffffff)
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(disableapertmacros false)
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(usegerberextensions false)
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(usegerberattributes false)
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(usegerberadvancedattributes false)
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(creategerberjobfile false)
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(svguseinch false)
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(svgprecision 6)
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(excludeedgelayer true)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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(dxfpolygonmode true)
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(dxfimperialunits true)
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(dxfusepcbnewfont true)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(sketchpadsonfab false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(net 1 "GND")
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(net 2 "+3V3")
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(net 3 "+5V")
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(net 4 "Net-(J1-Pad4)")
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(net 5 "/USB_D+")
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(net 6 "/USB_D-")
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(net 7 "Net-(IC1-Pad16)")
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(net 8 "Net-(IC1-Pad15)")
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(net 9 "Net-(IC1-Pad13)")
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(net 10 "Net-(IC1-Pad11)")
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(net 11 "Net-(IC1-Pad9)")
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(net 12 "Net-(IC1-Pad8)")
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(net 13 "Net-(IC1-Pad7)")
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(net 14 "Net-(IC1-Pad3)")
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(net 15 "Net-(IC1-Pad2)")
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(net 16 "/SDA")
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(net 17 "/SCL")
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(footprint "misc:USB_Micro-B" (layer "F.Cu")
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(tedit 58BB6CAC) (tstamp 00000000-0000-0000-0000-00005bc6c671)
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(at 119.6 114 -90)
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(descr "Micro USB Type B Receptacle")
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(tags "USB USB_B USB_micro USB_OTG")
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(path "/00000000-0000-0000-0000-00005bc9014b")
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(attr smd)
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(fp_text reference "J1" (at 0 -3.45 -90) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 19142c96-cd97-45b3-8b34-185d93a736d4)
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)
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(fp_text value "USB_B_Mini" (at 0 4.8 -90) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 591f07f5-9372-4cf1-aaf7-35a6c3e2f845)
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)
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(fp_line (start -4.3509 3.81746) (end -4.3509 -2.58754) (layer "F.SilkS") (width 0.15) (tstamp 30f49c3c-8dec-4a0d-ad60-118ffde39a76))
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(fp_line (start 4.3491 -2.58754) (end 4.3491 3.81746) (layer "F.SilkS") (width 0.15) (tstamp 7bad1388-06a8-492b-92c7-dd05fc82eb98))
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(fp_line (start -4.3509 3.81746) (end 4.3491 3.81746) (layer "F.SilkS") (width 0.15) (tstamp 82b7cd4d-7e2d-4496-acd4-d923e3c8b93c))
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(fp_line (start 4.3491 2.58746) (end -4.3509 2.58746) (layer "F.SilkS") (width 0.15) (tstamp b5138935-f4d8-4328-917a-9995721fc667))
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(fp_line (start -4.3509 -2.58754) (end 4.3491 -2.58754) (layer "F.SilkS") (width 0.15) (tstamp ce1d4461-bc7e-48f0-84a4-687a64887837))
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(fp_line (start 4.6 -2.8) (end 4.6 4.05) (layer "F.CrtYd") (width 0.05) (tstamp 17532c3f-7bcc-4906-bd41-ebf5e0831077))
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(fp_line (start -4.6 -2.8) (end 4.6 -2.8) (layer "F.CrtYd") (width 0.05) (tstamp 4796a32f-002e-449b-8fb2-c4108a118d80))
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(fp_line (start 4.6 4.05) (end -4.6 4.05) (layer "F.CrtYd") (width 0.05) (tstamp 783794ef-83f0-47ba-b2e9-66f7d9378127))
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(fp_line (start -4.6 4.05) (end -4.6 -2.8) (layer "F.CrtYd") (width 0.05) (tstamp e0959a58-2b7c-4a71-9f65-decd095bb440))
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||||||
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(pad "1" smd rect locked (at -1.3009 -1.56254) (size 1.35 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 3 "+5V") (tstamp 285f0e15-1598-43cc-9694-ef95b7f1c5a2))
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||||||
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(pad "2" smd rect locked (at -0.6509 -1.56254) (size 1.35 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 6 "/USB_D-") (tstamp 7934933f-6225-44c2-a670-7b29f03e51fb))
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||||||
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(pad "3" smd rect locked (at -0.0009 -1.56254) (size 1.35 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 5 "/USB_D+") (tstamp f0a66f8b-9c70-4c95-8f9e-68aff291bef7))
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(pad "4" smd rect locked (at 0.6491 -1.56254) (size 1.35 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 4 "Net-(J1-Pad4)") (zone_connect 1) (thermal_width 1) (thermal_gap 0.2) (tstamp 0045807b-9040-4aa2-8c99-82784cd811b8))
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(pad "5" smd rect locked (at 1.2991 -1.56254) (size 1.35 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 1 "GND") (zone_connect 1) (thermal_width 1) (thermal_gap 0.2) (tstamp c41b9a9d-6938-47b3-a6fe-2ed346c27eef))
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(pad "6" smd rect locked (at 3.75 1.15 270) (size 1.524 1.524) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 1 "GND") (tstamp 4347d612-d8f6-4214-94e2-8d259f248c3c))
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(pad "6" smd rect locked (at -3.75 1.15 270) (size 1.524 1.524) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 1 "GND") (tstamp d5d8c1e4-327b-42fc-bcef-3d0fa9018029))
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)
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(footprint "qfn:QFN-16_3x3mm_Pitch0.5mm" (layer "F.Cu")
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(tedit 5A98AF72) (tstamp 00000000-0000-0000-0000-00005bc84761)
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(at 148.1 123.8)
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(descr "16-Lead Plastic Quad Flat, No Lead Package (NG) - 3x3x0.9 mm Body [QFN]; (see Microchip Packaging Specification 00000049BS.pdf)")
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(tags "QFN 0.5")
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(path "/00000000-0000-0000-0000-00005bc741fc")
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(attr smd)
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(fp_text reference "IC1" (at 0 -2.85) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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||||||
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(tstamp 919cfb2a-4b33-4eaa-9fcf-f71c2db9ec0d)
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)
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||||||
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(fp_text value "MMA8452Q" (at 0 2.85) (layer "F.Fab")
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||||||
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(effects (font (size 1 1) (thickness 0.15)))
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(tstamp 1057c18a-2d26-415f-b6fe-b6a8a4e143de)
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)
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||||||
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(fp_line (start -1.625 1.625) (end -1.125 1.625) (layer "F.SilkS") (width 0.15) (tstamp 54d43383-b660-45c2-b859-23390872db24))
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(fp_line (start -1.625 1.625) (end -1.625 1.125) (layer "F.SilkS") (width 0.15) (tstamp 7f1cd3e9-0663-4ca9-8a1f-554ecd861cff))
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||||||
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(fp_line (start -1.625 -1.625) (end -1.125 -1.625) (layer "F.SilkS") (width 0.15) (tstamp 8d9a75a2-7a3a-4545-b43d-11bdb31e079c))
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(fp_line (start 1.625 1.625) (end 1.125 1.625) (layer "F.SilkS") (width 0.15) (tstamp a031b762-b06c-47a2-9495-7f23633424ec))
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(fp_line (start 1.625 -1.625) (end 1.625 -1.125) (layer "F.SilkS") (width 0.15) (tstamp be348632-6373-46e4-b04c-11fb88754b4f))
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(fp_line (start 1.625 -1.625) (end 1.125 -1.625) (layer "F.SilkS") (width 0.15) (tstamp cb75cd60-ed31-4f8e-939a-4de8b72598ed))
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(fp_line (start 1.625 1.625) (end 1.625 1.125) (layer "F.SilkS") (width 0.15) (tstamp e1a55277-0a9e-4a53-a61d-f416daa2acda))
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(fp_line (start -2.1 -2.1) (end -2.1 2.1) (layer "F.CrtYd") (width 0.05) (tstamp 3995023f-3760-4211-9568-a42f4e5e72eb))
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(fp_line (start -2.1 2.1) (end 2.1 2.1) (layer "F.CrtYd") (width 0.05) (tstamp 53846b37-01cd-4581-bb70-8275a9ac41e0))
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||||||
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(fp_line (start 2.1 -2.1) (end 2.1 2.1) (layer "F.CrtYd") (width 0.05) (tstamp 9749518f-e5f1-42c9-9e0e-5264dc9314a8))
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||||||
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(fp_line (start -2.1 -2.1) (end 2.1 -2.1) (layer "F.CrtYd") (width 0.05) (tstamp cab1b22d-525f-4ac8-b82d-72ce117fea45))
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||||||
|
(fp_line (start -1.5 1.5) (end -1.5 -0.5) (layer "F.Fab") (width 0.15) (tstamp 20aa9cb2-5d6d-4f8d-a070-499472cf19d9))
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||||||
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(fp_line (start -1.5 -0.5) (end -0.5 -1.5) (layer "F.Fab") (width 0.15) (tstamp 731eefa6-7315-4eab-b705-58c30105b493))
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||||||
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(fp_line (start -0.5 -1.5) (end 1.5 -1.5) (layer "F.Fab") (width 0.15) (tstamp a39a439e-0940-49fc-ab66-ac370492539e))
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||||||
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(fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer "F.Fab") (width 0.15) (tstamp db431869-db9d-4ba5-a193-2940ad858f13))
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||||||
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(fp_line (start 1.5 1.5) (end -1.5 1.5) (layer "F.Fab") (width 0.15) (tstamp faff729f-3e2f-4a0b-a63b-e906a9870a27))
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||||||
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(pad "1" smd oval locked (at -1.375 -1) (size 0.913 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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(net 2 "+3V3") (tstamp c65becca-4155-465d-8bda-b6350354aa2b))
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(pad "2" smd oval locked (at -1.375 -0.5) (size 0.913 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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(net 15 "Net-(IC1-Pad2)") (tstamp 8f8c614b-e364-44f4-91a9-6b3052ad5bea))
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||||||
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(pad "3" smd oval locked (at -1.375 0) (size 0.913 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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(net 14 "Net-(IC1-Pad3)") (tstamp 326cc9a4-5051-406c-8640-e4d273ea7994))
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||||||
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(pad "4" smd oval locked (at -1.375 0.5) (size 0.913 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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(net 17 "/SCL") (tstamp 2315ee17-8b32-4654-a4c0-60506183d7c8))
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||||||
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(pad "5" smd oval locked (at -1.375 1) (size 0.913 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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(net 1 "GND") (tstamp 93434739-9512-450f-9aff-96f54f812622))
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||||||
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(pad "6" smd oval locked (at -0.5 1.375 90) (size 0.93 0.3) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.024999999999999998,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
0.3,
|
||||||
|
0.35,
|
||||||
|
0.4
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 1.0,
|
||||||
|
"drill": 0.5
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"erc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "error",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "issue6417.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 36.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
"AM2315 sensors I2C interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
|
||||||
|
"230V & general interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
|
@ -0,0 +1,293 @@
|
||||||
|
(kicad_pcb (version 20171130) (host pcbnew "(5.1.0-rc2-38-g4612175da2)")
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
(drawings 0)
|
||||||
|
(tracks 7)
|
||||||
|
(zones 0)
|
||||||
|
(modules 1)
|
||||||
|
(nets 15)
|
||||||
|
)
|
||||||
|
|
||||||
|
(page A4)
|
||||||
|
(layers
|
||||||
|
(0 F.Cu signal)
|
||||||
|
(1 In1.Cu signal)
|
||||||
|
(2 In2.Cu signal)
|
||||||
|
(3 In3.Cu signal)
|
||||||
|
(4 In4.Cu signal)
|
||||||
|
(31 B.Cu signal)
|
||||||
|
(32 B.Adhes user)
|
||||||
|
(33 F.Adhes user)
|
||||||
|
(34 B.Paste user)
|
||||||
|
(35 F.Paste user)
|
||||||
|
(36 B.SilkS user)
|
||||||
|
(37 F.SilkS user)
|
||||||
|
(38 B.Mask user)
|
||||||
|
(39 F.Mask user)
|
||||||
|
(40 Dwgs.User user)
|
||||||
|
(41 Cmts.User user)
|
||||||
|
(42 Eco1.User user)
|
||||||
|
(43 Eco2.User user)
|
||||||
|
(44 Edge.Cuts user)
|
||||||
|
(45 Margin user)
|
||||||
|
(46 B.CrtYd user)
|
||||||
|
(47 F.CrtYd user)
|
||||||
|
(48 B.Fab user)
|
||||||
|
(49 F.Fab user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(last_trace_width 0.127)
|
||||||
|
(user_trace_width 0.1)
|
||||||
|
(user_trace_width 0.25)
|
||||||
|
(user_trace_width 0.5)
|
||||||
|
(user_trace_width 0.75)
|
||||||
|
(user_trace_width 1)
|
||||||
|
(user_trace_width 1.2)
|
||||||
|
(user_trace_width 1.65)
|
||||||
|
(user_trace_width 2.5)
|
||||||
|
(trace_clearance 0.12)
|
||||||
|
(zone_clearance 0.22)
|
||||||
|
(zone_45_only no)
|
||||||
|
(trace_min 0.09)
|
||||||
|
(via_size 0.45)
|
||||||
|
(via_drill 0.2)
|
||||||
|
(via_min_size 0.45)
|
||||||
|
(via_min_drill 0.2)
|
||||||
|
(user_via 0.45 0.2)
|
||||||
|
(uvia_size 0.2)
|
||||||
|
(uvia_drill 0.1)
|
||||||
|
(uvias_allowed no)
|
||||||
|
(uvia_min_size 0.2)
|
||||||
|
(uvia_min_drill 0.1)
|
||||||
|
(edge_width 0.15)
|
||||||
|
(segment_width 0.2)
|
||||||
|
(pcb_text_width 0.3)
|
||||||
|
(pcb_text_size 1.5 1.5)
|
||||||
|
(mod_edge_width 0.15)
|
||||||
|
(mod_text_size 0.5 0.5)
|
||||||
|
(mod_text_width 0.125)
|
||||||
|
(pad_size 0.3 0.5)
|
||||||
|
(pad_drill 0)
|
||||||
|
(pad_to_mask_clearance 0.0508)
|
||||||
|
(solder_mask_min_width 0.25)
|
||||||
|
(aux_axis_origin 0 0)
|
||||||
|
(visible_elements FFFDFF7F)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x010fc_ffffffff)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes false)
|
||||||
|
(usegerberadvancedattributes false)
|
||||||
|
(creategerberjobfile false)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(linewidth 0.100000)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(padsonsilk false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 0)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "."))
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 GND)
|
||||||
|
(net 2 /rasp_cm/HDMI_CK_N)
|
||||||
|
(net 3 /rasp_cm/HDMI_CK_P)
|
||||||
|
(net 4 /hdmi_conn/HDMI_D0_N)
|
||||||
|
(net 5 /hdmi_conn/HDMI_D0_P)
|
||||||
|
(net 6 /hdmi_conn/HDMI_D1_N)
|
||||||
|
(net 7 /hdmi_conn/HDMI_D1_P)
|
||||||
|
(net 8 /hdmi_conn/HDMI_D2_N)
|
||||||
|
(net 9 /hdmi_conn/HDMI_D2_P)
|
||||||
|
(net 10 /hdmi_conn/HDMI_CEC)
|
||||||
|
(net 11 /hdmi_conn/HDMI_SDA)
|
||||||
|
(net 12 /hdmi_conn/HDMI_SCL)
|
||||||
|
(net 13 /hdmi_conn/HDMI_HPD)
|
||||||
|
(net 14 +5V)
|
||||||
|
|
||||||
|
(net_class Default "This is the default net class."
|
||||||
|
(clearance 0.12)
|
||||||
|
(trace_width 0.127)
|
||||||
|
(via_dia 0.45)
|
||||||
|
(via_drill 0.2)
|
||||||
|
(uvia_dia 0.2)
|
||||||
|
(uvia_drill 0.1)
|
||||||
|
(diff_pair_width 0.2)
|
||||||
|
(diff_pair_gap 0.127)
|
||||||
|
(add_net +5V)
|
||||||
|
(add_net /hdmi_conn/HDMI_CEC)
|
||||||
|
(add_net /hdmi_conn/HDMI_D0_N)
|
||||||
|
(add_net /hdmi_conn/HDMI_D0_P)
|
||||||
|
(add_net /hdmi_conn/HDMI_D1_N)
|
||||||
|
(add_net /hdmi_conn/HDMI_D1_P)
|
||||||
|
(add_net /hdmi_conn/HDMI_D2_N)
|
||||||
|
(add_net /hdmi_conn/HDMI_D2_P)
|
||||||
|
(add_net /hdmi_conn/HDMI_HPD)
|
||||||
|
(add_net /hdmi_conn/HDMI_SCL)
|
||||||
|
(add_net /hdmi_conn/HDMI_SDA)
|
||||||
|
(add_net /rasp_cm/HDMI_CK_N)
|
||||||
|
(add_net /rasp_cm/HDMI_CK_P)
|
||||||
|
(add_net GND)
|
||||||
|
)
|
||||||
|
|
||||||
|
(module FS-Diode:TestFootprint (layer F.Cu) (tedit 5C7F02F0) (tstamp 5C7EF524)
|
||||||
|
(at 22.8 18.07 180)
|
||||||
|
(path /5B657F9C/5B658966)
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference U13 (at 0 1.8 180) (layer F.SilkS)
|
||||||
|
(effects (font (size 0.5 0.5) (thickness 0.125)))
|
||||||
|
)
|
||||||
|
(fp_text value TestFootprint (at 0 -1.7 180) (layer F.Fab)
|
||||||
|
(effects (font (size 0.5 0.5) (thickness 0.125)))
|
||||||
|
)
|
||||||
|
(fp_line (start -2.9 -0.9) (end -2.9 0.85) (layer F.SilkS) (width 0.15))
|
||||||
|
(fp_line (start -2.5 -0.9) (end -2.9 -0.9) (layer F.SilkS) (width 0.15))
|
||||||
|
(fp_line (start 2.9 -0.9) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
|
||||||
|
(fp_line (start 2.9 0.9) (end 2.9 -0.9) (layer F.SilkS) (width 0.15))
|
||||||
|
(fp_line (start 2.75 0.9) (end 2.9 0.9) (layer F.SilkS) (width 0.15))
|
||||||
|
(fp_line (start 2.75 0.75) (end 2.75 -0.75) (layer F.CrtYd) (width 0.15))
|
||||||
|
(fp_line (start 2.75 0.75) (end -2.75 0.75) (layer F.CrtYd) (width 0.15))
|
||||||
|
(fp_line (start -2.75 -0.75) (end -2.75 0.75) (layer F.CrtYd) (width 0.15))
|
||||||
|
(fp_line (start -2.75 -0.75) (end 2.75 -0.75) (layer F.CrtYd) (width 0.15))
|
||||||
|
(pad 15 smd rect (at 0 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 11 /hdmi_conn/HDMI_SDA))
|
||||||
|
(pad 14 smd rect (at 0.75 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 1 GND))
|
||||||
|
(pad 13 smd rect (at 1.5 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 14 +5V))
|
||||||
|
(pad 12 smd rect (at 2.25 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 1 GND))
|
||||||
|
(pad 16 smd rect (at -0.75 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 1 GND))
|
||||||
|
(pad 17 smd rect (at -1.5 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 10 /hdmi_conn/HDMI_CEC))
|
||||||
|
(pad 18 smd rect (at -2.25 -0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 1 GND))
|
||||||
|
(pad 6 smd rect (at 0 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 12 /hdmi_conn/HDMI_SCL))
|
||||||
|
(pad 7 smd rect (at 0.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 5 /hdmi_conn/HDMI_D0_P))
|
||||||
|
(pad 8 smd rect (at 1 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 4 /hdmi_conn/HDMI_D0_N))
|
||||||
|
(pad 9 smd rect (at 1.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 13 /hdmi_conn/HDMI_HPD))
|
||||||
|
(pad 10 smd rect (at 2 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 3 /rasp_cm/HDMI_CK_P))
|
||||||
|
(pad 11 smd rect (at 2.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 2 /rasp_cm/HDMI_CK_N))
|
||||||
|
(pad 5 smd rect (at -0.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 6 /hdmi_conn/HDMI_D1_N))
|
||||||
|
(pad 4 smd rect (at -1 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 7 /hdmi_conn/HDMI_D1_P))
|
||||||
|
(pad 3 smd rect (at -1.5 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask))
|
||||||
|
(pad 2 smd rect (at -2 0.65 180) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 8 /hdmi_conn/HDMI_D2_N))
|
||||||
|
(pad 1 smd rect (at -2.575 0.65 180) (size 0.45 0.5) (layers F.Cu F.Paste F.Mask)
|
||||||
|
(net 9 /hdmi_conn/HDMI_D2_P))
|
||||||
|
)
|
||||||
|
|
||||||
|
(segment (start 23.55 19.6) (end 23.55 19.6) (width 0.25) (layer F.Cu) (net 1))
|
||||||
|
(segment (start 23.141499 18.433671) (end 23.141499 19.996081) (width 0.127) (layer F.Cu) (net 6))
|
||||||
|
(segment (start 23.3 17.42) (end 23.3 18.27517) (width 0.127) (layer F.Cu) (net 6))
|
||||||
|
(segment (start 23.3 18.27517) (end 23.141499 18.433671) (width 0.127) (layer F.Cu) (net 6))
|
||||||
|
(segment (start 23.958501 18.458501) (end 23.958501 20.041499) (width 0.127) (layer F.Cu) (net 7))
|
||||||
|
(segment (start 23.8 17.42) (end 23.8 18.3) (width 0.127) (layer F.Cu) (net 7))
|
||||||
|
(segment (start 23.8 18.3) (end 23.958501 18.458501) (width 0.127) (layer F.Cu) (net 7))
|
||||||
|
|
||||||
|
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 5C7F0764) (hatch edge 0.508)
|
||||||
|
(connect_pads (clearance 0.2))
|
||||||
|
(min_thickness 0.254)
|
||||||
|
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
|
||||||
|
(polygon
|
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|
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@ -0,0 +1,633 @@
|
||||||
|
(kicad_pcb (version 20210722) (generator pcbnew)
|
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|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
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|
||||||
|
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|
||||||
|
(pcbplotparams
|
||||||
|
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|
||||||
|
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|
||||||
|
(usegerberextensions false)
|
||||||
|
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|
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@ -0,0 +1,184 @@
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{
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
|
@ -84,7 +84,7 @@
|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
|
|
|
@ -0,0 +1,445 @@
|
||||||
|
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|
|
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|
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|
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|
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|
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|
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|
||||||
|
|
||||||
|
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|
||||||
|
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|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
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|
||||||
|
(33 "F.Adhes" user)
|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
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|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
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|
||||||
|
|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
|
||||||
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||||||
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|
||||||
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|
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||||||
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|
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|
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|
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)
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|
@ -0,0 +1,155 @@
|
||||||
|
(kicad_pcb (version 20210722) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
(pad_to_mask_clearance 0)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "signal")
|
||||||
|
|
||||||
|
(footprint "Housings_DIP:DIP-14_W7.62mm_LongPads" (layer "F.Cu")
|
||||||
|
(tedit 61054ABB) (tstamp 3bd3a1e0-b35d-4974-99fa-33d3eee5d601)
|
||||||
|
(at 154.305 74.93)
|
||||||
|
(descr "14-lead dip package, row spacing 7.62 mm (300 mils), longer pads")
|
||||||
|
(tags "dil dip 2.54 300")
|
||||||
|
(attr through_hole)
|
||||||
|
(fp_text reference "REF**" (at 3.81 0) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 59609e9e-6f8e-414a-8e1a-68271157d0f4)
|
||||||
|
)
|
||||||
|
(fp_text value "DIP-14_W7.62mm_LongPads" (at 0 -3.72) (layer "F.Fab") hide
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 777520c7-f251-417a-a971-c4b28beed159)
|
||||||
|
)
|
||||||
|
(fp_line (start 0.135 17.535) (end 0.135 16.265) (layer "F.SilkS") (width 0.15) (tstamp 0b79ddb5-29b5-4d02-b254-210c2c0bc52a))
|
||||||
|
(fp_line (start 0.135 17.535) (end 7.485 17.535) (layer "F.SilkS") (width 0.15) (tstamp 0f83140d-7d8e-4df7-9004-7d55d208e970))
|
||||||
|
(fp_line (start 7.485 -2.295) (end 7.485 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 47d1c952-cc7e-48d8-8bf3-43e84030b5b6))
|
||||||
|
(fp_line (start 7.485 17.535) (end 7.485 16.265) (layer "F.SilkS") (width 0.15) (tstamp 4a6fe592-662f-4920-ac12-4fe3becc67da))
|
||||||
|
(fp_line (start 0.135 -1.025) (end -1.15 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 4c82108f-9f12-4804-907e-f81706f9251d))
|
||||||
|
(fp_line (start 0.135 -2.295) (end 7.485 -2.295) (layer "F.SilkS") (width 0.15) (tstamp e79a53c0-2b0d-4f45-9b3a-0d8f6a3f73f2))
|
||||||
|
(fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer "F.SilkS") (width 0.15) (tstamp fddf502b-35d9-4c79-83ea-e86b1347b469))
|
||||||
|
(fp_rect (start 2.286 0.127) (end 5.334 14.732) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp 1d78c688-c2db-4868-a03f-0436a459cbaf))
|
||||||
|
(fp_line (start 9 -2.45) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 2fe33ec7-1451-4a28-bf38-24c176dee936))
|
||||||
|
(fp_line (start -1.4 -2.45) (end -1.4 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 9873122d-04aa-4cf6-96df-5df12ef3440f))
|
||||||
|
(fp_line (start -1.4 -2.45) (end 9 -2.45) (layer "F.CrtYd") (width 0.05) (tstamp 9abef0ec-7068-4aa5-a4b2-c8cd8b0ceb6e))
|
||||||
|
(fp_line (start -1.4 17.7) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp c1c9a072-3005-4d0b-b7f6-70565ddfb731))
|
||||||
|
(pad "1" thru_hole oval locked (at 0 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 2fe6f3ef-3519-45f5-bd91-8d7847304292))
|
||||||
|
(pad "2" thru_hole oval locked (at 0 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 4f8caf82-f2fe-4ebb-b03c-0226aa886a96))
|
||||||
|
(pad "3" thru_hole oval locked (at 0 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp a01719d5-72b8-433b-882b-36b730f1b10d))
|
||||||
|
(pad "4" thru_hole oval locked (at 0 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask)
|
||||||
|
(net 1 "signal") (tstamp 7616ae07-fea3-41ec-baf7-0f401270819a))
|
||||||
|
(pad "5" thru_hole oval locked (at 0 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3443dd40-4950-45cf-ab02-9e2253c6bb3c))
|
||||||
|
(pad "6" thru_hole oval locked (at 0 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp cf6b8e1e-93f3-4e63-9f77-8c9ec064201c))
|
||||||
|
(pad "7" thru_hole oval locked (at 0 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp f522aabe-6821-4dcd-853d-a284f451356d))
|
||||||
|
(pad "8" thru_hole oval locked (at 7.62 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp db0b3374-d270-4249-87b7-9a0a6163297e))
|
||||||
|
(pad "9" thru_hole oval locked (at 7.62 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 07dd9b8f-a4b6-4b90-9868-4559ed6f6a32))
|
||||||
|
(pad "10" thru_hole oval locked (at 7.62 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 036d5919-6a4b-49ac-851e-0b99804de700))
|
||||||
|
(pad "11" thru_hole oval locked (at 7.62 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 54ecef87-4bce-44eb-93cf-a1f86ce2bb62))
|
||||||
|
(pad "12" thru_hole oval locked (at 7.62 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 2f3483f5-a99f-4f68-b6b1-fe893d5ab874))
|
||||||
|
(pad "13" thru_hole oval locked (at 7.62 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 30760006-239e-48b2-9ad2-bdc85ca119ed))
|
||||||
|
(pad "14" thru_hole oval locked (at 7.62 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp fefb1ddf-3d2b-4862-9521-565bc091912b))
|
||||||
|
(model "Housings_DIP.3dshapes/DIP-14_W7.62mm_LongPads.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_rect (start 78.105 50.165) (end 228.6 130.81) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp d0d883cf-992c-40b1-8baf-44f8b31bd338))
|
||||||
|
(gr_text "One" (at 133.35 64.77) (layer "F.SilkS") (tstamp 0e48904b-ea9c-4e28-ae84-906127f78887)
|
||||||
|
(effects (font (size 2 2) (thickness 0.3)))
|
||||||
|
)
|
||||||
|
(gr_text "Two" (at 137.795 66.675) (layer "F.SilkS") (tstamp 683b3cc8-60dd-4ae9-b579-b6f37d1dfd82)
|
||||||
|
(effects (font (size 2 2) (thickness 0.3)))
|
||||||
|
)
|
||||||
|
(gr_text "Fully outside" (at 180.975 45.72) (layer "F.SilkS") (tstamp 9fd9af26-80f4-4ca8-8f38-17afe2252638)
|
||||||
|
(effects (font (size 3 3) (thickness 0.5)))
|
||||||
|
)
|
||||||
|
(gr_text "Clipped by board edge" (at 154.305 51.435) (layer "F.SilkS") (tstamp cf5bcf24-ec78-4346-ae94-9ab700e3d44d)
|
||||||
|
(effects (font (size 3 3) (thickness 0.5)))
|
||||||
|
)
|
||||||
|
|
||||||
|
)
|
|
@ -0,0 +1,486 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": true,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 2,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": true,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": true,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.8,
|
||||||
|
"height": 1.6,
|
||||||
|
"width": 2.3
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": true,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.19999999999999998
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "error",
|
||||||
|
"silk_overlap": "error",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.09999999999999999,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
0.2,
|
||||||
|
0.4,
|
||||||
|
1.0,
|
||||||
|
2.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": [
|
||||||
|
{
|
||||||
|
"activeLayer": -2,
|
||||||
|
"layers": [
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
6,
|
||||||
|
7,
|
||||||
|
8,
|
||||||
|
9,
|
||||||
|
10,
|
||||||
|
11,
|
||||||
|
12,
|
||||||
|
13,
|
||||||
|
14,
|
||||||
|
15,
|
||||||
|
16,
|
||||||
|
17,
|
||||||
|
18,
|
||||||
|
19,
|
||||||
|
20,
|
||||||
|
21,
|
||||||
|
22,
|
||||||
|
23,
|
||||||
|
24,
|
||||||
|
25,
|
||||||
|
26,
|
||||||
|
27,
|
||||||
|
28,
|
||||||
|
29,
|
||||||
|
30,
|
||||||
|
41,
|
||||||
|
44,
|
||||||
|
49,
|
||||||
|
50
|
||||||
|
],
|
||||||
|
"name": "Fabrication",
|
||||||
|
"renderLayers": [
|
||||||
|
125,
|
||||||
|
126,
|
||||||
|
127,
|
||||||
|
128,
|
||||||
|
129,
|
||||||
|
130,
|
||||||
|
131,
|
||||||
|
133,
|
||||||
|
134,
|
||||||
|
135,
|
||||||
|
136,
|
||||||
|
137,
|
||||||
|
138,
|
||||||
|
139,
|
||||||
|
143,
|
||||||
|
144
|
||||||
|
]
|
||||||
|
}
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "LoRaNode.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.25,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "antenna",
|
||||||
|
"nets": [
|
||||||
|
"/ANTENNA"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 1.27,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "[",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "]",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "./",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"285a99a7-a1a2-4aa6-812b-d3c3533a57d7",
|
||||||
|
""
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8236a8",
|
||||||
|
"battery-protection"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8260b7",
|
||||||
|
"voltage-regulation"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d825820",
|
||||||
|
"RS485-interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d84b44c",
|
||||||
|
"I2C-interface"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
|
@ -57,7 +57,7 @@
|
||||||
],
|
],
|
||||||
"drc_exclusions": [],
|
"drc_exclusions": [],
|
||||||
"meta": {
|
"meta": {
|
||||||
"version": 1
|
"version": 2
|
||||||
},
|
},
|
||||||
"rule_severities": {
|
"rule_severities": {
|
||||||
"annular_width": "error",
|
"annular_width": "error",
|
||||||
|
@ -85,7 +85,7 @@
|
||||||
"padstack": "error",
|
"padstack": "error",
|
||||||
"pth_inside_courtyard": "ignore",
|
"pth_inside_courtyard": "ignore",
|
||||||
"shorting_items": "error",
|
"shorting_items": "error",
|
||||||
"silk_over_copper": "error",
|
"silk_over_copper": "ignore",
|
||||||
"silk_overlap": "error",
|
"silk_overlap": "error",
|
||||||
"skew_out_of_range": "error",
|
"skew_out_of_range": "error",
|
||||||
"too_many_vias": "error",
|
"too_many_vias": "error",
|
||||||
|
|
|
@ -0,0 +1,16 @@
|
||||||
|
(version 1)
|
||||||
|
|
||||||
|
(rule "PTH to Track Clearance"
|
||||||
|
(constraint hole_clearance (min 1.0mm))
|
||||||
|
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "NPTH to Track Clearance"
|
||||||
|
(constraint hole_clearance (min 1.0mm))
|
||||||
|
(condition "(A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical') && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Max Drill Hole Size Mechanical"
|
||||||
|
(constraint hole (max 2.0mm))
|
||||||
|
(condition "A.Type == 'Pad'")
|
||||||
|
)
|
|
@ -0,0 +1,508 @@
|
||||||
|
(kicad_pcb (version 20201220) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "Net-(C1-Pad2)")
|
||||||
|
(net 2 "Net-(C1-Pad1)")
|
||||||
|
|
||||||
|
(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad" (layer "F.Cu")
|
||||||
|
(tedit 56D1B4CB) (tstamp 7a5e0185-cb99-4816-a212-1cb5fdda6fe8)
|
||||||
|
(at 186.25 88.75)
|
||||||
|
(descr "Mounting Hole 3.2mm, M3, DIN965")
|
||||||
|
(tags "mounting hole 3.2mm m3 din965")
|
||||||
|
(property "Sheet file" "Test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/fb2e017d-a5c5-49fb-ba95-cb396aae3918")
|
||||||
|
(attr exclude_from_pos_files)
|
||||||
|
(fp_text reference "H3" (at 0 4) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 600b29e3-3ea7-48fd-a954-b81d7d21815f)
|
||||||
|
)
|
||||||
|
(fp_text value "PTH-3mm" (at 0 3.8) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 982881b5-77b1-4780-b97a-b48fc7c793a6)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 1710c190-e24b-4590-9dd6-c08f5a3e6148)
|
||||||
|
)
|
||||||
|
(fp_circle (center 0 0) (end 2.8 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp 533cb978-4c67-4904-86ed-173bc2ff1b45))
|
||||||
|
(fp_circle (center 0 0) (end 3.05 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp c08b7dbb-612b-43e9-a6cc-d4e66c1ea404))
|
||||||
|
(pad "1" thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask) (tstamp cfbc907d-8a25-46e9-a224-6b8152fa214f))
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad" (layer "F.Cu")
|
||||||
|
(tedit 56D1B4CB) (tstamp 7effd7e7-a352-4b60-90dc-d04da9924f3e)
|
||||||
|
(at 166.25 88.75)
|
||||||
|
(descr "Mounting Hole 3.2mm, M3, DIN965")
|
||||||
|
(tags "mounting hole 3.2mm m3 din965")
|
||||||
|
(property "Sheet file" "Test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/01326b80-c3a1-4c72-b881-eee45cdb68c5")
|
||||||
|
(attr exclude_from_pos_files)
|
||||||
|
(fp_text reference "H4" (at 0 4) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 3dfd39dc-326f-4ebf-a42f-a5544836a15a)
|
||||||
|
)
|
||||||
|
(fp_text value "PTH-3mm" (at 0 3.8) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp bbec47e3-9ffa-4d68-9bd8-d2c50951193f)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp ba466aa3-f900-4724-b154-de8778c10cec)
|
||||||
|
)
|
||||||
|
(fp_circle (center 0 0) (end 2.8 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp 7f8e2e3b-3a66-47a9-a58a-28516317d286))
|
||||||
|
(fp_circle (center 0 0) (end 3.05 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp ee76c024-e387-4561-9d80-268c0015a52b))
|
||||||
|
(pad "1" thru_hole circle (at 0 0) (size 5.6 5.6) (drill 3.2) (layers *.Cu *.Mask) (tstamp b5c3eb60-d01c-403e-abf7-cd1ddd2c14be))
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu")
|
||||||
|
(tedit 56D1B4CB) (tstamp b155e8e6-593a-4fdd-b7be-b9cbbe47b854)
|
||||||
|
(at 166.25 111)
|
||||||
|
(descr "Mounting Hole 3.2mm, no annular, M3")
|
||||||
|
(tags "mounting hole 3.2mm no annular m3")
|
||||||
|
(property "Sheet file" "Test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/9c1f6247-3f70-4646-bb3c-a8c45bbfc056")
|
||||||
|
(attr exclude_from_pos_files)
|
||||||
|
(fp_text reference "H2" (at 0 -4.2) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp ccc0899b-bbf2-4044-9984-8b8b6c30c83f)
|
||||||
|
)
|
||||||
|
(fp_text value "NPTH-3mm" (at 0 4.2) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp b473fa3b-3b92-4646-b990-3a686d714123)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp d71db0be-3896-4a51-beac-40768d8d3ef1)
|
||||||
|
)
|
||||||
|
(fp_circle (center 0 0) (end 3.2 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp d4901f12-4dae-4cd4-9bb1-5d962ba4e57d))
|
||||||
|
(fp_circle (center 0 0) (end 3.45 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 3d371e65-4ed5-435b-8cfc-b2bca6d607db))
|
||||||
|
(pad "1" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask) (tstamp 30bed439-ee98-4fbc-9d75-6c7a47f1e483))
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "MountingHole:MountingHole_3.2mm_M3" (layer "F.Cu")
|
||||||
|
(tedit 56D1B4CB) (tstamp dd6e559d-f8e5-4209-a83a-cd7404d50c5d)
|
||||||
|
(at 186.25 111)
|
||||||
|
(descr "Mounting Hole 3.2mm, no annular, M3")
|
||||||
|
(tags "mounting hole 3.2mm no annular m3")
|
||||||
|
(property "Sheet file" "Test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/e0c75322-6681-4b92-9d80-a5c2e61fb79f")
|
||||||
|
(attr exclude_from_pos_files)
|
||||||
|
(fp_text reference "H1" (at 0 -4.2) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 5b6ed842-a876-4bd0-8f81-70bdfe998dc6)
|
||||||
|
)
|
||||||
|
(fp_text value "NPTH-3mm" (at 0 4.2) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp fa284b56-4b5e-4ac6-bcab-b929f46c97c6)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0.3 0) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 5054f0ca-f585-4ee1-a91e-658ca5387bf2)
|
||||||
|
)
|
||||||
|
(fp_circle (center 0 0) (end 3.2 0) (layer "Cmts.User") (width 0.15) (fill none) (tstamp ad1a6974-bb9c-4845-bf1b-4eb349a7b5f9))
|
||||||
|
(fp_circle (center 0 0) (end 3.45 0) (layer "F.CrtYd") (width 0.05) (fill none) (tstamp 7495fc84-6ec6-45ca-9071-d10637312859))
|
||||||
|
(pad "1" np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask) (tstamp 3c6562ef-6330-45e0-b952-0a82c3116b50))
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical" (layer "F.Cu")
|
||||||
|
(tedit 5C28146C) (tstamp e918d824-8add-477a-bc72-c18e218465c7)
|
||||||
|
(at 165.5 101.25 90)
|
||||||
|
(descr "JST XH series connector, B2B-XH-A (http://www.jst-mfg.com/product/pdf/eng/eXH.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "connector JST XH vertical")
|
||||||
|
(property "LCSC N°" "C20079")
|
||||||
|
(property "N°" "XH-2A")
|
||||||
|
(property "Sheet file" "Test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/73dee3db-4043-47b4-b8c7-6ed59b861244")
|
||||||
|
(attr through_hole)
|
||||||
|
(fp_text reference "J1" (at -3.75 -2 180) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp f9009f25-1208-4105-9f60-1e769861c0b9)
|
||||||
|
)
|
||||||
|
(fp_text value "XH-2A" (at 1.25 4.6 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 5addb007-8ec3-4029-b4b3-109887a8afbf)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 1.25 2.7 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp aa56998b-ed2f-428f-b788-3cb40902350a)
|
||||||
|
)
|
||||||
|
(fp_line (start 1.75 -1.7) (end 1.75 -2.45) (layer "F.SilkS") (width 0.12) (tstamp 0adc786e-c434-4492-a65f-ea2dbf023bbb))
|
||||||
|
(fp_line (start 3.25 -2.45) (end 3.25 -1.7) (layer "F.SilkS") (width 0.12) (tstamp 0d7ef226-df0e-4ed6-9909-f4b0f354bab3))
|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
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(offset (xyz 0 0 0))
|
||||||
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|
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|
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)
|
||||||
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)
|
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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||||||
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||||||
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|
||||||
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|
||||||
|
|
||||||
|
)
|
|
@ -0,0 +1,394 @@
|
||||||
|
{
|
||||||
|
"board": {
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
}
|
||||||
|
},
|
||||||
|
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|
||||||
|
{
|
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|
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|
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|
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|
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|
}
|
||||||
|
],
|
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|
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|
||||||
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|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"track_dangling": "warning",
|
||||||
|
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|
||||||
|
"tracks_crossing": "error",
|
||||||
|
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|
||||||
|
"unresolved_variable": "error",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
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|
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|
||||||
|
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|
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|
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|
||||||
|
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|
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|
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|
||||||
|
"min_via_diameter": 0.6,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"solder_paste_margin_ratio": -0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
1.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
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|
{
|
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|
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|
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|
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|
||||||
|
}
|
||||||
|
],
|
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|
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|
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|
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|
||||||
|
},
|
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|
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|
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|
},
|
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|
"boards": [],
|
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|
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|
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|
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|
||||||
|
},
|
||||||
|
"erc": {
|
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|
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|
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"pin_map": [
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[
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||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "Test.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 6.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"8f39686c-273b-419b-9330-c9f7a9a20c4d",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
|
@ -0,0 +1,61 @@
|
||||||
|
(version 1)
|
||||||
|
(rule "Distance between 1mm test points"
|
||||||
|
(constraint courtyard_clearance (min 1.54mm))
|
||||||
|
(condition "A.Reference =='TP*' && B.Reference == 'TP*")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Distance between Vias Hole Same Nets"
|
||||||
|
(constraint hole_to_hole (min 0.254mm))
|
||||||
|
(condition "A.Type =='Via' && B.Type =='Via' && A.Net == B.Net")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Distance between Vias Hole Different Nets"
|
||||||
|
(constraint hole_to_hole (min 0.5mm))
|
||||||
|
(condition "A.Type =='Via' && B.Type =='Via' && A.Net != B.Net")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Via Hole to Track Clearance"
|
||||||
|
(constraint hole_clearance (min 0.254mm))
|
||||||
|
(condition "A.Type =='Via' && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Pad to Track Clearance"
|
||||||
|
(constraint clearance (min 0.2mm))
|
||||||
|
(condition "A.Type =='Pad' && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Distance between Pads Hole Same Nets"
|
||||||
|
(constraint hole_to_hole (min 0.254mm))
|
||||||
|
(condition "A.Type =='Pad' && B.Type =='Pad' && A.Net == B.Net")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Distance between Pads Hole Different Nets"
|
||||||
|
(constraint hole_to_hole (min 0.50mm))
|
||||||
|
(condition "A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "PTH to Track Clearance"
|
||||||
|
(constraint hole_clearance (min 0.33mm))
|
||||||
|
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "NPTH to Track Clearance"
|
||||||
|
(constraint hole_clearance (min 0.254mm))
|
||||||
|
(condition "(A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical') && B.Type =='Track'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Max Drill Hole Size Mechanical"
|
||||||
|
(constraint hole (max 6.3mm))
|
||||||
|
(condition "A.Pad_Type == 'NPTH, mechanical'")
|
||||||
|
)
|
||||||
|
|
||||||
|
(rule "Max Drill Hole Size PTH"
|
||||||
|
(constraint hole (max 6.35mm))
|
||||||
|
(condition "A.Pad_Type == 'Through-hole'")
|
||||||
|
)
|
||||||
|
|
||||||
|
#TEST
|
||||||
|
(rule "Disallow via in testpoint pad"
|
||||||
|
(constraint disallow via)
|
||||||
|
(condition "A.insideCourtyard('TP*')")
|
||||||
|
)
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,84 @@
|
||||||
|
(kicad_pcb (version 20210722) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(pad_to_mask_clearance 0)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
|
||||||
|
(gr_rect (start 78.105 50.165) (end 228.6 130.81) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp d0d883cf-992c-40b1-8baf-44f8b31bd338))
|
||||||
|
(gr_text "Text should generate DRC warning...." (at 202.565 119.38) (layer "Edge.Cuts") (tstamp dc3e6522-5d53-4f8e-b319-7cf9c7db49ec)
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
)
|
||||||
|
|
||||||
|
)
|
|
@ -0,0 +1,149 @@
|
||||||
|
(kicad_pcb (version 20210722) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
(pad_to_mask_clearance 0)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "signal")
|
||||||
|
|
||||||
|
(footprint "Housings_DIP:DIP-14_W7.62mm_LongPads" (layer "F.Cu")
|
||||||
|
(tedit 6105426B) (tstamp 3bd3a1e0-b35d-4974-99fa-33d3eee5d601)
|
||||||
|
(at 154.305 74.93)
|
||||||
|
(descr "14-lead dip package, row spacing 7.62 mm (300 mils), longer pads")
|
||||||
|
(tags "dil dip 2.54 300")
|
||||||
|
(attr through_hole)
|
||||||
|
(fp_text reference "REF**" (at 0 -5.22) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 59609e9e-6f8e-414a-8e1a-68271157d0f4)
|
||||||
|
)
|
||||||
|
(fp_text value "DIP-14_W7.62mm_LongPads" (at 0 -3.72) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 777520c7-f251-417a-a971-c4b28beed159)
|
||||||
|
)
|
||||||
|
(fp_line (start 0.135 17.535) (end 0.135 16.265) (layer "F.SilkS") (width 0.15) (tstamp 0b79ddb5-29b5-4d02-b254-210c2c0bc52a))
|
||||||
|
(fp_line (start 0.135 17.535) (end 7.485 17.535) (layer "F.SilkS") (width 0.15) (tstamp 0f83140d-7d8e-4df7-9004-7d55d208e970))
|
||||||
|
(fp_line (start 7.485 -2.295) (end 7.485 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 47d1c952-cc7e-48d8-8bf3-43e84030b5b6))
|
||||||
|
(fp_line (start 7.485 17.535) (end 7.485 16.265) (layer "F.SilkS") (width 0.15) (tstamp 4a6fe592-662f-4920-ac12-4fe3becc67da))
|
||||||
|
(fp_line (start 0.135 -1.025) (end -1.15 -1.025) (layer "F.SilkS") (width 0.15) (tstamp 4c82108f-9f12-4804-907e-f81706f9251d))
|
||||||
|
(fp_line (start 0.135 -2.295) (end 7.485 -2.295) (layer "F.SilkS") (width 0.15) (tstamp e79a53c0-2b0d-4f45-9b3a-0d8f6a3f73f2))
|
||||||
|
(fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer "F.SilkS") (width 0.15) (tstamp fddf502b-35d9-4c79-83ea-e86b1347b469))
|
||||||
|
(fp_rect (start 2.286 0.127) (end 5.334 14.732) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp 1d78c688-c2db-4868-a03f-0436a459cbaf))
|
||||||
|
(fp_line (start 9 -2.45) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 2fe33ec7-1451-4a28-bf38-24c176dee936))
|
||||||
|
(fp_line (start -1.4 -2.45) (end -1.4 17.7) (layer "F.CrtYd") (width 0.05) (tstamp 9873122d-04aa-4cf6-96df-5df12ef3440f))
|
||||||
|
(fp_line (start -1.4 -2.45) (end 9 -2.45) (layer "F.CrtYd") (width 0.05) (tstamp 9abef0ec-7068-4aa5-a4b2-c8cd8b0ceb6e))
|
||||||
|
(fp_line (start -1.4 17.7) (end 9 17.7) (layer "F.CrtYd") (width 0.05) (tstamp c1c9a072-3005-4d0b-b7f6-70565ddfb731))
|
||||||
|
(pad "1" thru_hole oval locked (at 0 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 2fe6f3ef-3519-45f5-bd91-8d7847304292))
|
||||||
|
(pad "2" thru_hole oval locked (at 0 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 4f8caf82-f2fe-4ebb-b03c-0226aa886a96))
|
||||||
|
(pad "3" thru_hole oval locked (at 0 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp a01719d5-72b8-433b-882b-36b730f1b10d))
|
||||||
|
(pad "4" thru_hole oval locked (at 0 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask)
|
||||||
|
(net 1 "signal") (tstamp 7616ae07-fea3-41ec-baf7-0f401270819a))
|
||||||
|
(pad "5" thru_hole oval locked (at 0 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 3443dd40-4950-45cf-ab02-9e2253c6bb3c))
|
||||||
|
(pad "6" thru_hole oval locked (at 0 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp cf6b8e1e-93f3-4e63-9f77-8c9ec064201c))
|
||||||
|
(pad "7" thru_hole oval locked (at 0 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp f522aabe-6821-4dcd-853d-a284f451356d))
|
||||||
|
(pad "8" thru_hole oval locked (at 7.62 15.24) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp db0b3374-d270-4249-87b7-9a0a6163297e))
|
||||||
|
(pad "9" thru_hole oval locked (at 7.62 12.7) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 07dd9b8f-a4b6-4b90-9868-4559ed6f6a32))
|
||||||
|
(pad "10" thru_hole oval locked (at 7.62 10.16) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 036d5919-6a4b-49ac-851e-0b99804de700))
|
||||||
|
(pad "11" thru_hole oval locked (at 7.62 7.62) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 54ecef87-4bce-44eb-93cf-a1f86ce2bb62))
|
||||||
|
(pad "12" thru_hole oval locked (at 7.62 5.08) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask)
|
||||||
|
(net 1 "signal") (tstamp 2f3483f5-a99f-4f68-b6b1-fe893d5ab874))
|
||||||
|
(pad "13" thru_hole oval locked (at 7.62 2.54) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 30760006-239e-48b2-9ad2-bdc85ca119ed))
|
||||||
|
(pad "14" thru_hole oval locked (at 7.62 0) (size 2.3 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp fefb1ddf-3d2b-4862-9521-565bc091912b))
|
||||||
|
(model "Housings_DIP.3dshapes/DIP-14_W7.62mm_LongPads.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_rect (start 78.105 50.165) (end 228.6 130.81) (layer "Edge.Cuts") (width 0.05) (fill none) (tstamp d0d883cf-992c-40b1-8baf-44f8b31bd338))
|
||||||
|
|
||||||
|
(segment (start 159.385 80.01) (end 156.845 82.55) (width 0.25) (layer "F.Cu") (net 1) (tstamp 21b5daa4-e65f-4e1c-a333-2091740a1e4a))
|
||||||
|
(segment (start 156.845 82.55) (end 154.305 82.55) (width 0.25) (layer "F.Cu") (net 1) (tstamp 3d3d3243-6bbc-49ec-beed-2a25912450f2))
|
||||||
|
(segment (start 161.925 80.01) (end 238.125 80.01) (width 0.25) (layer "F.Cu") (net 1) (tstamp 621611c9-2b28-46fa-ba36-db611bc29586))
|
||||||
|
(segment (start 161.925 80.01) (end 159.385 80.01) (width 0.25) (layer "F.Cu") (net 1) (tstamp d3322cbe-61d2-451b-b61a-efdb757a7742))
|
||||||
|
|
||||||
|
)
|
|
@ -0,0 +1,427 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.0,
|
||||||
|
"copper_text_size_v": 1.0,
|
||||||
|
"copper_text_thickness": 0.19999999999999998,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 2,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 1,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 0.8128,
|
||||||
|
"fab_text_size_v": 0.8128,
|
||||||
|
"fab_text_thickness": 0.15239999999999998,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 0.8128,
|
||||||
|
"other_text_size_v": 0.8128,
|
||||||
|
"other_text_thickness": 0.15239999999999998,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 3.2,
|
||||||
|
"height": 6.0,
|
||||||
|
"width": 6.0
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15239999999999998,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 0.8128,
|
||||||
|
"silk_text_size_v": 0.8128,
|
||||||
|
"silk_text_thickness": 0.15239999999999998,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.2032
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "warning",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "ignore",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.2032,
|
||||||
|
"min_copper_edge_clearance": 0.19999999999999998,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.15,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.2032,
|
||||||
|
"min_via_annular_width": 0.15,
|
||||||
|
"min_via_diameter": 0.6,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_paste_clearance": 0.0,
|
||||||
|
"solder_paste_margin_ratio": -0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
0.2032,
|
||||||
|
0.254,
|
||||||
|
0.3048,
|
||||||
|
0.4064,
|
||||||
|
0.508,
|
||||||
|
0.6096,
|
||||||
|
0.8128,
|
||||||
|
1.016,
|
||||||
|
1.27,
|
||||||
|
1.524,
|
||||||
|
1.778,
|
||||||
|
2.032,
|
||||||
|
2.286,
|
||||||
|
2.54
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.6,
|
||||||
|
"drill": 0.3
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.7,
|
||||||
|
"drill": 0.4
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
"drill": 0.5
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"erc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "error",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "020.02.010.0221.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2032,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2032,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 36.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
"AM2315 sensors I2C interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
|
||||||
|
"230V & general interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
|
@ -0,0 +1,7 @@
|
||||||
|
#(version 1.0)
|
||||||
|
#(rule silk2via
|
||||||
|
# (constraint silk_clearance(min 0.15mm))
|
||||||
|
# (condition "A.Type=='*Text' && B.Type=='Via'"))
|
||||||
|
#(rule silk2via1
|
||||||
|
#(constraint silk_clearance(min 0.15mm))
|
||||||
|
#(condition "A.Type=='Graphic*' && B.Type=='Via'"))
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,427 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.0,
|
||||||
|
"copper_text_size_v": 1.0,
|
||||||
|
"copper_text_thickness": 0.19999999999999998,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 2,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 1,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 0.8128,
|
||||||
|
"fab_text_size_v": 0.8128,
|
||||||
|
"fab_text_thickness": 0.15239999999999998,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 0.8128,
|
||||||
|
"other_text_size_v": 0.8128,
|
||||||
|
"other_text_thickness": 0.15239999999999998,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 3.2,
|
||||||
|
"height": 6.0,
|
||||||
|
"width": 6.0
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15239999999999998,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 0.8128,
|
||||||
|
"silk_text_size_v": 0.8128,
|
||||||
|
"silk_text_thickness": 0.15239999999999998,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.2032
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "ignore",
|
||||||
|
"silk_overlap": "warning",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.2032,
|
||||||
|
"min_copper_edge_clearance": 0.19999999999999998,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.15,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.2032,
|
||||||
|
"min_via_annular_width": 0.15,
|
||||||
|
"min_via_diameter": 0.6,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_paste_clearance": 0.0,
|
||||||
|
"solder_paste_margin_ratio": -0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.0,
|
||||||
|
0.2032,
|
||||||
|
0.254,
|
||||||
|
0.3048,
|
||||||
|
0.4064,
|
||||||
|
0.508,
|
||||||
|
0.6096,
|
||||||
|
0.8128,
|
||||||
|
1.016,
|
||||||
|
1.27,
|
||||||
|
1.524,
|
||||||
|
1.778,
|
||||||
|
2.032,
|
||||||
|
2.286,
|
||||||
|
2.54
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.0,
|
||||||
|
"drill": 0.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.6,
|
||||||
|
"drill": 0.3
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.7,
|
||||||
|
"drill": 0.4
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
"drill": 0.5
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"erc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "warning",
|
||||||
|
"no_connect_dangling": "warning",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "error",
|
||||||
|
"power_pin_not_driven": "error",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "020.02.010.0221.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2032,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2032,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 36.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
"AM2315 sensors I2C interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"3171c8e1-e8bd-4b55-9726-8c0ea0490320",
|
||||||
|
"230V & general interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"155f8eea-0e5f-4cd4-af54-d2a6a7cc5844",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
|
@ -0,0 +1,9 @@
|
||||||
|
(version 1)
|
||||||
|
(rule "keepout holes"
|
||||||
|
(constraint disallow hole)
|
||||||
|
(condition "A.insideArea('NoBottomFootprints')" )
|
||||||
|
)
|
||||||
|
(rule "keepout bottom footprints"
|
||||||
|
(constraint disallow pad)
|
||||||
|
(condition "A.Layer_Bottom && A.insideArea('NoBottomFootprints')" )
|
||||||
|
)
|
|
@ -0,0 +1,343 @@
|
||||||
|
(kicad_pcb (version 20210126) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
(aux_axis_origin 96.52 144.78)
|
||||||
|
(grid_origin 96.52 144.78)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00000fc_80000001)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes false)
|
||||||
|
(usegerberadvancedattributes false)
|
||||||
|
(creategerberjobfile false)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 0)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "GND")
|
||||||
|
(net 2 "+5V")
|
||||||
|
(net 3 "+3V3")
|
||||||
|
(net 4 "GPIO_SPI_CS#")
|
||||||
|
(net 5 "GPIO_UART1_TXD")
|
||||||
|
(net 6 "GPIO_SPI_MISO")
|
||||||
|
(net 7 "GPIO_UART1_RXD")
|
||||||
|
(net 8 "GPIO_SPI_MOSI")
|
||||||
|
(net 9 "GPIO_UART1_CTS")
|
||||||
|
(net 10 "GPIO_SPI_CLK")
|
||||||
|
(net 11 "GPIO_UART1_RTS")
|
||||||
|
(net 12 "GPIO_I2C_SCL")
|
||||||
|
(net 13 "GPIO_I2S_CLK")
|
||||||
|
(net 14 "GPIO_I2C_SDA")
|
||||||
|
(net 15 "GPIO_I2S_FRM")
|
||||||
|
(net 16 "GPIO_UART2_TXD")
|
||||||
|
(net 17 "GPIO_I2S_DO")
|
||||||
|
(net 18 "GPIO_UART2_RXD")
|
||||||
|
(net 19 "GPIO_I2S_DI")
|
||||||
|
(net 20 "GPIO_S5_0")
|
||||||
|
(net 21 "GPIO_PWM0")
|
||||||
|
(net 22 "GPIO_S5_1")
|
||||||
|
(net 23 "GPIO_PWM1")
|
||||||
|
(net 24 "GPIO_S5_2")
|
||||||
|
(net 25 "I2SMCLK_GPIO")
|
||||||
|
|
||||||
|
(footprint "Pin_Headers:Pin_Header_Straight_2x13" locked (layer "F.Cu")
|
||||||
|
(tedit 577F1E14) (tstamp 00000000-0000-0000-0000-000057710c62)
|
||||||
|
(at 109.855 142.24 90)
|
||||||
|
(descr "Through hole pin header")
|
||||||
|
(tags "pin header")
|
||||||
|
(path "/00000000-0000-0000-0000-0000576c994f")
|
||||||
|
(attr through_hole)
|
||||||
|
(fp_text reference "P1" (at 1.27 -3.175 90) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp df6ea7ea-4c97-406e-b3d5-74ea4b56d842)
|
||||||
|
)
|
||||||
|
(fp_text value "CONN_02X13" (at 5.08 3.175 180) (layer "F.Fab") hide
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 0521fa67-7953-4a88-8d72-df0659d06791)
|
||||||
|
)
|
||||||
|
(fp_line (start 3.81 31.75) (end -1.27 31.75) (layer "F.SilkS") (width 0.15) (tstamp 30162e69-e978-4092-8abd-fb8cf99fe5ab))
|
||||||
|
(fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer "F.SilkS") (width 0.15) (tstamp 3167fff6-db1d-4c63-8d24-a011d71fcd96))
|
||||||
|
(fp_line (start -1.27 1.27) (end -1.27 31.75) (layer "F.SilkS") (width 0.15) (tstamp 4ec22dd7-3cbb-4efa-95a5-9b85d3a13668))
|
||||||
|
(fp_line (start -1.55 -1.55) (end -1.55 0) (layer "F.SilkS") (width 0.15) (tstamp 520abb36-f693-4622-b926-5fd5e9d9c40f))
|
||||||
|
(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer "F.SilkS") (width 0.15) (tstamp 76480a74-d043-445b-9be1-34656ab0d843))
|
||||||
|
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer "F.SilkS") (width 0.15) (tstamp 8ca8e6ad-651f-477d-a59c-8edaf8b2b42c))
|
||||||
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|
||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
|
(pad "2" thru_hole oval (at 2.54 0 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 1 "GND") (tstamp da748863-9757-41e5-820a-7f527a6b67f4))
|
||||||
|
(pad "3" thru_hole oval (at 0 2.54 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 2 "+5V") (tstamp 5e5f556f-b431-451a-97db-c239bfdb6b76))
|
||||||
|
(pad "4" thru_hole oval (at 2.54 2.54 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 3 "+3V3") (tstamp 3549d9b3-8d6e-45c8-9dc8-155d51b3f1f4))
|
||||||
|
(pad "5" thru_hole oval (at 0 5.08 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 4 "GPIO_SPI_CS#") (tstamp bb0fbcdb-2c6a-42d9-b77d-949cc4808960))
|
||||||
|
(pad "6" thru_hole oval (at 2.54 5.08 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 5 "GPIO_UART1_TXD") (tstamp 12b020e9-d4e0-43a5-806a-e9106735ab66))
|
||||||
|
(pad "7" thru_hole oval (at 0 7.62 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 6 "GPIO_SPI_MISO") (tstamp 7693013d-863f-442e-99fb-6039d8b588de))
|
||||||
|
(pad "8" thru_hole oval (at 2.54 7.62 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 7 "GPIO_UART1_RXD") (tstamp bc5ffcde-e33e-441d-b6ac-3e6afc4d94e7))
|
||||||
|
(pad "9" thru_hole oval (at 0 10.16 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 8 "GPIO_SPI_MOSI") (tstamp 7f45ed09-d0b5-4fac-9eb4-20ee6c6f07a5))
|
||||||
|
(pad "10" thru_hole oval (at 2.54 10.16 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 9 "GPIO_UART1_CTS") (tstamp 98154aac-31dc-461f-bfc2-29e338d032b8))
|
||||||
|
(pad "11" thru_hole oval (at 0 12.7 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 10 "GPIO_SPI_CLK") (tstamp fe7b12bd-1172-47eb-89b1-4e16aee85fab))
|
||||||
|
(pad "12" thru_hole oval (at 2.54 12.7 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 11 "GPIO_UART1_RTS") (tstamp f205cafc-4bc4-4231-937b-c32e5ee0917f))
|
||||||
|
(pad "13" thru_hole oval (at 0 15.24 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 12 "GPIO_I2C_SCL") (tstamp 0d650c51-94a2-4a05-b514-dcca6c661b70))
|
||||||
|
(pad "14" thru_hole oval (at 2.54 15.24 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 13 "GPIO_I2S_CLK") (tstamp 62385088-5982-4c59-83ee-a3e784b8dcc6))
|
||||||
|
(pad "15" thru_hole oval (at 0 17.78 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 14 "GPIO_I2C_SDA") (tstamp 13faa25d-676b-4b52-bb43-20b12e4ee67b))
|
||||||
|
(pad "16" thru_hole oval (at 2.54 17.78 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 15 "GPIO_I2S_FRM") (tstamp 12e0b964-6275-4d6d-bc8e-1115d1e67dd0))
|
||||||
|
(pad "17" thru_hole oval (at 0 20.32 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 16 "GPIO_UART2_TXD") (tstamp e6f77aad-8f77-428b-b3da-8b4736e0a396))
|
||||||
|
(pad "18" thru_hole oval (at 2.54 20.32 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 17 "GPIO_I2S_DO") (tstamp 456b7b6c-732b-4dd9-bb8c-bbfb8fd8ea8c))
|
||||||
|
(pad "19" thru_hole oval (at 0 22.86 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
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|
||||||
|
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|
||||||
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(net 19 "GPIO_I2S_DI") (tstamp 31a6a5b8-e9b4-41b0-be22-3a2ae05ecc51))
|
||||||
|
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|
||||||
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|
||||||
|
(pad "22" thru_hole oval (at 2.54 25.4 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
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||||||
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|
||||||
|
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||||||
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|
||||||
|
(pad "24" thru_hole oval (at 2.54 27.94 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
(net 23 "GPIO_PWM1") (tstamp 376a7697-de73-4228-b597-7420574cb8f4))
|
||||||
|
(pad "25" thru_hole oval (at 0 30.48 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
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||||||
|
(net 24 "GPIO_S5_2") (tstamp ad3c0573-42eb-4ab4-acec-a839887126ca))
|
||||||
|
(pad "26" thru_hole oval (at 2.54 30.48 90) (locked) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask "F.SilkS")
|
||||||
|
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|
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|
(model "Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl"
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|
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|
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|
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|
||||||
|
|
||||||
|
(footprint "Mounting_Holes:MountingHole_3-5mm" locked (layer "F.Cu")
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|
(tedit 58633422) (tstamp 00000000-0000-0000-0000-0000577da462)
|
||||||
|
(at 191.77 140.97)
|
||||||
|
(descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
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(tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
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||||||
|
(at 100.33 140.97)
|
||||||
|
(descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
|
||||||
|
(tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
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||||||
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(tedit 58633440) (tstamp 00000000-0000-0000-0000-0000577f1cb9)
|
||||||
|
(at 100.33 74.93)
|
||||||
|
(descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
|
||||||
|
(tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
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||||||
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)
|
||||||
|
|
||||||
|
(footprint "Mounting_Holes:MountingHole_3-5mm" locked (layer "F.Cu")
|
||||||
|
(tedit 58633432) (tstamp 00000000-0000-0000-0000-0000577f1cc4)
|
||||||
|
(at 191.77 74.93)
|
||||||
|
(descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
|
||||||
|
(tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
|
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|
||||||
|
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|
||||||
|
|
||||||
|
(footprint "Resistor_SMD:R_0201_0603Metric" (layer "F.Cu")
|
||||||
|
(tedit 5B301BBD) (tstamp c6d657fd-5fb9-4795-b35b-b8b571ac9973)
|
||||||
|
(at 108.52 103.78)
|
||||||
|
(descr "Resistor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator")
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)
|
||||||
|
|
||||||
|
(gr_line (start 195.58 71.12) (end 96.52 71.12) (angle 90) (layer "Edge.Cuts") (width 0.15) (tstamp 2668eae5-e838-4dec-a87d-2b40a098a0a2))
|
||||||
|
(gr_line (start 96.52 144.78) (end 195.58 144.78) (angle 90) (layer "Edge.Cuts") (width 0.15) (tstamp 4db5a4c9-4072-41cd-a257-fadcefa47294))
|
||||||
|
(gr_line (start 195.58 144.78) (end 195.58 71.12) (angle 90) (layer "Edge.Cuts") (width 0.15) (tstamp c5eebce5-78a3-4142-8902-e211c6cd5c8f))
|
||||||
|
(gr_line (start 96.52 71.12) (end 96.52 144.78) (angle 90) (layer "Edge.Cuts") (width 0.15) (tstamp deb9b139-58fd-49d8-9b12-09ad44d4f842))
|
||||||
|
(target plus (at 96.52 144.78) (size 5) (width 0.15) (layer "Edge.Cuts") (tstamp 0656fbe8-d593-4158-9bf3-80d6a1b2e6a0))
|
||||||
|
|
||||||
|
(zone (net 0) (net_name "") (layer "B.Cu") (tstamp 7ecf5a8d-7053-4645-8dde-8ebe3d86d387) (name "NoBottomFootprints") (hatch full 0.508)
|
||||||
|
(connect_pads (clearance 0))
|
||||||
|
(min_thickness 0.254)
|
||||||
|
(keepout (tracks allowed) (vias allowed) (pads allowed ) (copperpour allowed) (footprints allowed))
|
||||||
|
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
|
||||||
|
(polygon
|
||||||
|
(pts
|
||||||
|
(xy 114.96 110.15)
|
||||||
|
(xy 96.52 110.15)
|
||||||
|
(xy 96.52 92.05)
|
||||||
|
(xy 114.96 92.05)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(zone (net 0) (net_name "") (layer "B.Cu") (tstamp a318326d-41b9-4ad1-a1b1-e90c920d74a2) (name "NoBottomFootprints") (hatch full 0.508)
|
||||||
|
(connect_pads (clearance 0))
|
||||||
|
(min_thickness 0.254)
|
||||||
|
(keepout (tracks allowed) (vias allowed) (pads allowed ) (copperpour allowed) (footprints not_allowed))
|
||||||
|
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508))
|
||||||
|
(polygon
|
||||||
|
(pts
|
||||||
|
(xy 195.58 112.02)
|
||||||
|
(xy 178.86 112.02)
|
||||||
|
(xy 178.86 96.83)
|
||||||
|
(xy 195.58 96.83)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
|
@ -0,0 +1,176 @@
|
||||||
|
(kicad_pcb (version 20210228) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(pad_to_mask_clearance 0)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x00010fc_ffffffff)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes true)
|
||||||
|
(usegerberadvancedattributes true)
|
||||||
|
(creategerberjobfile true)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(dxfpolygonmode true)
|
||||||
|
(dxfimperialunits true)
|
||||||
|
(dxfusepcbnewfont true)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "/NET_B")
|
||||||
|
(net 2 "/NET_A")
|
||||||
|
|
||||||
|
(footprint "Resistor_SMD:R_1206_3216Metric" (layer "F.Cu")
|
||||||
|
(tedit 5F68FEEE) (tstamp b68b261f-f4c9-4eef-9ff6-988c61cc3af7)
|
||||||
|
(at 141.351 78.867 90)
|
||||||
|
(descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "resistor")
|
||||||
|
(property "Sheetfile" "drc4.kicad_sch")
|
||||||
|
(property "Sheetname" "")
|
||||||
|
(path "/9a8b5393-bbd4-45fa-9ab2-b594d7c05cb6")
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference "R1" (at 0.127 2.0574 90) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 254bdf2d-d49b-452a-9897-795d9599eed4)
|
||||||
|
)
|
||||||
|
(fp_text value "10k" (at 0 1.82 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 1865a67d-1664-4d96-911b-938a14f746b9)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 0.8 0.8) (thickness 0.12)))
|
||||||
|
(tstamp 4a9b9b15-194c-4782-8e95-78cb930f8c9b)
|
||||||
|
)
|
||||||
|
(fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer "F.SilkS") (width 0.12) (tstamp b0089ac4-7bc4-4525-92d3-216f60e81c1d))
|
||||||
|
(fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer "F.SilkS") (width 0.12) (tstamp ddde4b4e-5356-4156-b6cc-8a7f3eb720cf))
|
||||||
|
(fp_line (start -2.28 -1.12) (end 2.28 -1.12) (layer "F.CrtYd") (width 0.05) (tstamp 6b778cda-fdd8-4407-b62a-093e677637f9))
|
||||||
|
(fp_line (start 2.28 -1.12) (end 2.28 1.12) (layer "F.CrtYd") (width 0.05) (tstamp da85902f-328c-42c8-aeb4-473134dff5da))
|
||||||
|
(fp_line (start 2.28 1.12) (end -2.28 1.12) (layer "F.CrtYd") (width 0.05) (tstamp f5e73456-a50d-4267-a859-b88b4cdcdb42))
|
||||||
|
(fp_line (start -2.28 1.12) (end -2.28 -1.12) (layer "F.CrtYd") (width 0.05) (tstamp ffc540a3-0864-46af-8164-c3b19b9eb622))
|
||||||
|
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer "F.Fab") (width 0.1) (tstamp 31a251c4-fd62-4958-9ad2-c98c1c153758))
|
||||||
|
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer "F.Fab") (width 0.1) (tstamp 57c6cf04-f25a-4eb2-89c5-bfc561cc28c2))
|
||||||
|
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer "F.Fab") (width 0.1) (tstamp d646a40a-faef-4906-b541-818321c1a58a))
|
||||||
|
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer "F.Fab") (width 0.1) (tstamp e5f2a5e0-5af2-409c-a9cd-236a55b46972))
|
||||||
|
(pad "1" smd roundrect (at -1.4625 0 90) (locked) (size 1.125 1.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.222222)
|
||||||
|
(net 2 "/NET_A") (pintype "passive") (tstamp c69de6ad-e39a-4788-a757-b7516dce18a6))
|
||||||
|
(pad "2" smd roundrect (at 1.4625 0 90) (locked) (size 1.125 1.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.222222)
|
||||||
|
(net 1 "/NET_B") (pintype "passive") (tstamp 64df41cd-249a-44e2-8ece-db9044298f6e))
|
||||||
|
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "Resistor_SMD:R_1206_3216Metric" (layer "F.Cu")
|
||||||
|
(tedit 5F68FEEE) (tstamp f14ef839-68d9-418e-ad16-64736560725d)
|
||||||
|
(at 135.509 77.851 90)
|
||||||
|
(descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "resistor")
|
||||||
|
(property "Sheetfile" "drc4.kicad_sch")
|
||||||
|
(property "Sheetname" "")
|
||||||
|
(path "/03610aed-5c3d-40b0-978d-59519cfeb402")
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference "R2" (at 0 -1.82 90) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 986e4117-8fd6-4956-92bc-2f11fcba2513)
|
||||||
|
)
|
||||||
|
(fp_text value "10k" (at 0 1.82 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp efd356e0-9fbc-4eba-b41e-a09ea03128ed)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 0.8 0.8) (thickness 0.12)))
|
||||||
|
(tstamp 809a3f4f-871d-42c0-933f-934021ed715d)
|
||||||
|
)
|
||||||
|
(fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer "F.SilkS") (width 0.12) (tstamp 4292c661-4eb3-43f7-8718-8c91a9e1637b))
|
||||||
|
(fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer "F.SilkS") (width 0.12) (tstamp e82654a8-5bfa-4229-b151-0284374c6ca9))
|
||||||
|
(fp_line (start 2.28 -1.12) (end 2.28 1.12) (layer "F.CrtYd") (width 0.05) (tstamp 00dd09e3-562c-4a68-9c39-97744c61c9a6))
|
||||||
|
(fp_line (start -2.28 -1.12) (end 2.28 -1.12) (layer "F.CrtYd") (width 0.05) (tstamp 7f96b14e-a999-4d90-8ae1-42c1ffcc021f))
|
||||||
|
(fp_line (start -2.28 1.12) (end -2.28 -1.12) (layer "F.CrtYd") (width 0.05) (tstamp 8b9c1d99-4b8f-4fe7-a139-663a2b2adcea))
|
||||||
|
(fp_line (start 2.28 1.12) (end -2.28 1.12) (layer "F.CrtYd") (width 0.05) (tstamp 9e84a299-c391-455a-9f9f-d7bdd5e6ee8a))
|
||||||
|
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer "F.Fab") (width 0.1) (tstamp 03355848-54f2-498d-8fb4-ad0472fb93da))
|
||||||
|
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer "F.Fab") (width 0.1) (tstamp 3f7c3a19-588e-4554-93de-0acd855f92a0))
|
||||||
|
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer "F.Fab") (width 0.1) (tstamp 751ae58c-818d-4189-9578-8d12393fb4de))
|
||||||
|
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer "F.Fab") (width 0.1) (tstamp d3c0f7ad-d7da-4987-b647-5585bf5137b3))
|
||||||
|
(pad "1" smd roundrect (at -1.4625 0 90) (locked) (size 1.125 1.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.222222)
|
||||||
|
(net 2 "/NET_A") (pintype "passive") (tstamp a202d05d-6123-4f3b-83ac-e9b52ab59302))
|
||||||
|
(pad "2" smd roundrect (at 1.4625 0 90) (locked) (size 1.125 1.75) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.222222)
|
||||||
|
(net 1 "/NET_B") (pintype "passive") (tstamp 79a76fdb-bb70-453e-9d81-12637b5ac88f))
|
||||||
|
(model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_rect (start 130.9624 74.1426) (end 145.669 82.3976) (layer "Edge.Cuts") (width 0.1) (fill none) (tstamp 08c0673b-d188-4c34-917e-8882ac6e1e61))
|
||||||
|
|
||||||
|
(segment (start 137.6025 76.3885) (end 138.6185 77.4045) (width 0.25) (layer "F.Cu") (net 1) (tstamp 4fafb321-75ab-428f-a223-7df9a10734e0))
|
||||||
|
(segment (start 138.6185 77.4045) (end 141.351 77.4045) (width 0.25) (layer "F.Cu") (net 1) (tstamp b14a6fe5-b108-4eb0-874f-5289bbab5bfa))
|
||||||
|
(segment (start 135.509 76.3885) (end 137.6025 76.3885) (width 0.25) (layer "F.Cu") (net 1) (tstamp d3626667-3ba8-4618-aa74-3caa02344256))
|
||||||
|
(segment (start 139.848946 79.3135) (end 135.509 79.3135) (width 0.25) (layer "F.Cu") (net 2) (tstamp 2eeacdee-4d9d-4c65-bec0-86c0df177b61))
|
||||||
|
(segment (start 141.351 80.3295) (end 141.351 78.1812) (width 0.25) (layer "F.Cu") (net 2) (tstamp cc9b6272-14ca-4190-9739-bbef74b465c0))
|
||||||
|
(segment (start 139.858023 79.304423) (end 139.848946 79.3135) (width 0.25) (layer "F.Cu") (net 2) (tstamp cf2dd366-898e-44f5-a25d-72ceb10e7a23))
|
||||||
|
(segment (start 141.351 78.1812) (end 139.858023 79.304423) (width 0.25) (layer "F.Cu") (net 2) (tstamp d9381e5d-0866-4d83-ad66-159c2205cc99))
|
||||||
|
|
||||||
|
)
|
|
@ -56,21 +56,25 @@ struct DRC_REGRESSION_TEST_FIXTURE
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
||||||
std::string projectPath = absPath + ".kicad_pro";
|
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||||
std::string boardPath = absPath + ".kicad_pcb";
|
std::string boardPath = absPath + ".kicad_pcb";
|
||||||
|
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||||
|
|
||||||
wxFileName pro( projectPath );
|
if( projectFile.Exists() )
|
||||||
|
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
||||||
if( pro.Exists() )
|
|
||||||
m_settingsManager.LoadProject( pro.GetFullPath() );
|
|
||||||
|
|
||||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
||||||
|
|
||||||
if( pro.Exists() )
|
if( projectFile.Exists() )
|
||||||
m_board->SetProject( &m_settingsManager.Prj() );
|
m_board->SetProject( &m_settingsManager.Prj() );
|
||||||
|
|
||||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
||||||
m_DRCEngine->InitEngine( wxFileName() );
|
|
||||||
|
if( rulesFile.Exists() )
|
||||||
|
m_DRCEngine->InitEngine( rulesFile );
|
||||||
|
else
|
||||||
|
m_DRCEngine->InitEngine( wxFileName() );
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||||
|
|
||||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
||||||
|
@ -105,15 +109,20 @@ BOOST_FIXTURE_TEST_SUITE( TestDRCRegressions, DRC_REGRESSION_TEST_FIXTURE )
|
||||||
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
||||||
|
|
||||||
|
|
||||||
BOOST_AUTO_TEST_CASE( DRCRegressions )
|
BOOST_AUTO_TEST_CASE( DRCFalsePositiveRegressions )
|
||||||
{
|
{
|
||||||
for( const wxString& relPath : { "issue4139",
|
// These documents at one time flagged DRC errors that they shouldn't have.
|
||||||
"issue4774",
|
|
||||||
"issue5978",
|
std::vector<wxString> tests = { "issue4139",
|
||||||
"issue5990",
|
"issue4774",
|
||||||
"issue6443",
|
"issue5978",
|
||||||
"issue7975",
|
"issue5990",
|
||||||
"issue8407" } )
|
"issue6443",
|
||||||
|
"issue7567",
|
||||||
|
"issue7975",
|
||||||
|
"issue8407" };
|
||||||
|
|
||||||
|
for( const wxString& relPath : tests )
|
||||||
{
|
{
|
||||||
loadBoard( relPath );
|
loadBoard( relPath );
|
||||||
fillZones( 6 );
|
fillZones( 6 );
|
||||||
|
@ -121,8 +130,8 @@ BOOST_AUTO_TEST_CASE( DRCRegressions )
|
||||||
std::vector<DRC_ITEM> violations;
|
std::vector<DRC_ITEM> violations;
|
||||||
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_WARNING;
|
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||||
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_WARNING;
|
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_IGNORE;
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
m_DRCEngine->SetViolationHandler(
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
|
@ -133,17 +142,76 @@ BOOST_AUTO_TEST_CASE( DRCRegressions )
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, %s",
|
if( violations.empty() )
|
||||||
relPath,
|
{
|
||||||
violations.empty() ? "passed" : "failed" ) );
|
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", relPath ) );
|
||||||
|
}
|
||||||
if( !violations.empty() )
|
else
|
||||||
{
|
{
|
||||||
std::map<KIID, EDA_ITEM*> itemMap;
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
m_board->FillItemMap( itemMap );
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
for( const DRC_ITEM& item : violations )
|
for( const DRC_ITEM& item : violations )
|
||||||
BOOST_ERROR( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
|
{
|
||||||
|
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||||
|
itemMap ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_ERROR( wxString::Format( "DRC regression: %s, failed", relPath ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_AUTO_TEST_CASE( DRCFalseNegativeRegressions )
|
||||||
|
{
|
||||||
|
// These documents at one time failed to catch DRC errors that they should have.
|
||||||
|
|
||||||
|
std::vector< std::pair<wxString, int> > tests = { { "issue1358", 2 },
|
||||||
|
{ "issue2528", 1 },
|
||||||
|
{ "issue5750", 4 },
|
||||||
|
{ "issue5854", 3 },
|
||||||
|
{ "issue6879", 6 },
|
||||||
|
{ "issue6945", 2 },
|
||||||
|
{ "issue7241", 1 },
|
||||||
|
{ "issue7267", 4 },
|
||||||
|
{ "issue7325", 21 },
|
||||||
|
{ "issue8003", 2 } };
|
||||||
|
|
||||||
|
for( const std::pair<wxString, int>& entry : tests )
|
||||||
|
{
|
||||||
|
loadBoard( entry.first );
|
||||||
|
fillZones( 6 );
|
||||||
|
|
||||||
|
std::vector<DRC_ITEM> violations;
|
||||||
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
|
m_DRCEngine->SetViolationHandler(
|
||||||
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
|
{
|
||||||
|
violations.push_back( *aItem );
|
||||||
|
} );
|
||||||
|
|
||||||
|
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
|
if( violations.size() == entry.second )
|
||||||
|
{
|
||||||
|
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, passed", entry.first ) );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BOOST_CHECK_EQUAL( violations.size(), entry.second );
|
||||||
|
|
||||||
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
|
for( const DRC_ITEM& item : violations )
|
||||||
|
{
|
||||||
|
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||||
|
itemMap ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_ERROR( wxString::Format( "DRC regression: %s, failed", entry.first ) );
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -56,21 +56,25 @@ struct ZONE_FILL_TEST_FIXTURE
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
std::string absPath = KI_TEST::GetPcbnewTestDataDir() + relPath.ToStdString();
|
||||||
std::string projectPath = absPath + ".kicad_pro";
|
wxFileName projectFile( absPath + ".kicad_pro" );
|
||||||
std::string boardPath = absPath + ".kicad_pcb";
|
std::string boardPath = absPath + ".kicad_pcb";
|
||||||
|
wxFileName rulesFile( absPath + ".kicad_dru" );
|
||||||
|
|
||||||
wxFileName pro( projectPath );
|
if( projectFile.Exists() )
|
||||||
|
m_settingsManager.LoadProject( projectFile.GetFullPath() );
|
||||||
if( pro.Exists() )
|
|
||||||
m_settingsManager.LoadProject( pro.GetFullPath() );
|
|
||||||
|
|
||||||
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
||||||
|
|
||||||
if( pro.Exists() )
|
if( projectFile.Exists() )
|
||||||
m_board->SetProject( &m_settingsManager.Prj() );
|
m_board->SetProject( &m_settingsManager.Prj() );
|
||||||
|
|
||||||
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
||||||
m_DRCEngine->InitEngine( wxFileName() );
|
|
||||||
|
if( rulesFile.Exists() )
|
||||||
|
m_DRCEngine->InitEngine( rulesFile );
|
||||||
|
else
|
||||||
|
m_DRCEngine->InitEngine( wxFileName() );
|
||||||
|
|
||||||
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||||
|
|
||||||
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
||||||
|
@ -233,16 +237,20 @@ BOOST_AUTO_TEST_CASE( NotchedZones )
|
||||||
|
|
||||||
BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
|
BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
|
||||||
{
|
{
|
||||||
for( const wxString& relPath : { "issue2568",
|
std::vector<wxString> tests = { "issue18",
|
||||||
"issue3812",
|
"issue2568",
|
||||||
"issue5102",
|
"issue3812",
|
||||||
"issue5320",
|
"issue5102",
|
||||||
"issue5567",
|
"issue5313",
|
||||||
"issue5830",
|
"issue5320",
|
||||||
"issue6039",
|
"issue5567",
|
||||||
"issue6260",
|
"issue5830",
|
||||||
"issue6284",
|
"issue6039",
|
||||||
"issue7086" } )
|
"issue6260",
|
||||||
|
"issue6284",
|
||||||
|
"issue7086" };
|
||||||
|
|
||||||
|
for( const wxString& relPath : tests )
|
||||||
{
|
{
|
||||||
loadBoard( relPath );
|
loadBoard( relPath );
|
||||||
|
|
||||||
|
@ -261,18 +269,26 @@ BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d fill algo %s",
|
if( violations.empty() )
|
||||||
relPath,
|
{
|
||||||
fillVersion,
|
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d algo passed",
|
||||||
violations.empty() ? "passed" : "failed" ) );
|
relPath,
|
||||||
|
fillVersion ) );
|
||||||
if( !violations.empty() )
|
}
|
||||||
|
else
|
||||||
{
|
{
|
||||||
std::map<KIID, EDA_ITEM*> itemMap;
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
m_board->FillItemMap( itemMap );
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
for( const DRC_ITEM& v : violations )
|
for( const DRC_ITEM& item : violations )
|
||||||
BOOST_ERROR( v.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
|
{
|
||||||
|
BOOST_TEST_MESSAGE( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR,
|
||||||
|
itemMap ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_ERROR( wxString::Format( "Zone fill regression: %s, V%d algo failed",
|
||||||
|
relPath,
|
||||||
|
fillVersion ) );
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue