More flexible node mapping in Spice netlist exporter
Allows to map nodes to pins for Spice models that have more pins than corresponding schematic symbol. An example is a MOSFET model containing gate, source, drain & body, whereas schematic symbol part has only gate, source & drain with body and source connected inside the part.
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@ -94,38 +94,21 @@ bool NETLIST_EXPORTER_PSPICE::Format( OUTPUTFORMATTER* aFormatter, unsigned aCtl
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if( !item.m_enabled )
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continue;
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// Save the node order
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aFormatter->Print( 0, "%c%s ", item.m_primitive, (const char*) item.m_refName.c_str() );
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// Pins to node mapping
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int activePinIndex = 0;
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size_t pspiceNodes = item.m_pinSequence.empty() ? item.m_pins.size() : item.m_pinSequence.size();
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for( unsigned ii = 0; ii < item.m_pins.size(); ii++ )
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for( size_t ii = 0; ii < pspiceNodes; ii++ )
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{
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// Case of Alt Sequence definition with Unused/Invalid Node index:
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// Use the custom order if defined, otherwise use the standard pin order as defined in the compon
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size_t activePinIndex = item.m_pinSequence.empty() ? ii : item.m_pinSequence[ii];
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// Valid used Node Indexes are in the set
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// {0,1,2,...m_item.m_pin.size()-1}
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if( !item.m_pinSequence.empty() )
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if( activePinIndex >= item.m_pins.size() )
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{
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// All Vector values must be less <= max package size
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// And Total Vector size should be <= package size
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if( ( (unsigned) item.m_pinSequence[ii] < item.m_pins.size() )
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&& ( ii < item.m_pinSequence.size() ) )
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{
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// Case of Alt Pin Sequence in control good Index:
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activePinIndex = item.m_pinSequence[ii];
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}
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else
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{
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// Case of Alt Pin Sequence in control Bad Index or not using all
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// pins for simulation:
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wxASSERT_MSG( false, "Used an invalid pin number in node sequence" );
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continue;
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}
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}
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// Case of Standard Pin Sequence in control:
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else
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{
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activePinIndex = ii;
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wxASSERT_MSG( false, "Used an invalid pin number in node sequence" );
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continue;
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}
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NETLIST_OBJECT* pin = item.m_pins[activePinIndex];
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