drc_proto: netclass wip

qa/CMakeLists.txt

@@ -62,3 +62,4 @@ add_subdirectory( pcbnew_tools )
 
 # add_subdirectory( pcb_test_window )
 add_subdirectory( gal/gal_pixel_alignment )
+

qa/drc_proto/drc_engine.cpp

@@ -297,9 +297,25 @@ void test::DRC_ENGINE::inferLegacyRules()
 
     std::vector<NETCLASS_ENTRY> netclassesByClearance, netclassesByWidth;
 
+    m_board->SynchronizeNetsAndNetClasses();
+
+    // fixme: make this conditional for standalone tests
+    bds.SetNetClasses( nullptr ); // load legacy
+
+    std::vector<NETCLASSPTR> netclasses;
+
+    netclasses.push_back( bds.GetNetClasses().GetDefault() );
+    
+    for( auto netclass : bds.GetNetClasses() )
+        netclasses.push_back( netclass.second );
+
+    ReportAux( wxString::Format( "Importing %d legacy net classes", (int) netclasses.size() ) );
+
+#if 0
     for( auto netclass : bds.GetNetClasses() )
     {
         auto className = netclass.second->GetName();
+        drc_dbg(1,"Process netclass '%s'\n", className );
         NETCLASS_ENTRY ent;
         ent.name = className;
         ent.clearance = netclass.second->GetClearance();
@@ -319,12 +335,17 @@ void test::DRC_ENGINE::inferLegacyRules()
     {
         return a.width > b.width;
     } );
+#endif
     
 
-
+#if 0
     for( int i = 0; i <  netclassesByClearance.size(); i++ )
     {
-        wxString className = netclassesByClearance[i].name;
+#endif
+    int i = 0;
+    for( auto &nc : netclasses )
+    {
+        wxString className = nc->GetName();
 
         const auto expr = wxString::Format( "A.NetClass == '%s' || B.NetClass == '%s'", className, className );
 
@@ -336,25 +357,25 @@ void test::DRC_ENGINE::inferLegacyRules()
         netclassRule->SetCondition( inNetclassCondition );
 
         DRC_CONSTRAINT ncClearanceConstraint ( DRC_CONSTRAINT_TYPE_CLEARANCE );
-        ncClearanceConstraint.Value().SetMin( netclassesByClearance[i].clearance );
+        ncClearanceConstraint.Value().SetMin( nc->GetClearance() );
         netclassRule->AddConstraint( ncClearanceConstraint );
 
-        className = netclassesByWidth[i].name;
-
         netclassRule = createInferredRule( wxString::Format( "inferred-netclass-width-%s", className ),
             {}, priorityRangeMin + i );
 
         netclassRule->SetCondition( inNetclassCondition );
 
         DRC_CONSTRAINT ncWidthConstraint ( DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
-        ncWidthConstraint.Value().SetMin( netclassesByWidth[i].width );
+        ncWidthConstraint.Value().SetMin( nc->GetTrackWidth() );
         netclassRule->AddConstraint( ncWidthConstraint );
 
         // TODO: should we import diff pair gaps/widths here?
+        i++;
     }
 
 
 
+
     //clearanceConstraint.SetMin( )
 
     //rule->AddConstraint( )

qa/drc_proto/drc_proto_test.cpp

@@ -34,6 +34,10 @@
 #include <reporter.h>
 #include <widgets/progress_reporter.h>
 
+#include <project.h>
+#include <settings/settings_manager.h>
+#include <wildcards_and_files_ext.h>
+
 class CONSOLE_LOG
 {
 public:
@@ -154,6 +158,32 @@ private:
     CONSOLE_LOG* m_log;
 };
 
+
+struct PROJECT_CONTEXT {
+    PROJECT* project;
+    std::shared_ptr<BOARD> board;
+};
+
+SETTINGS_MANAGER g_settingsManager( true );
+
+PROJECT_CONTEXT loadKicadProject( wxString filename )
+{
+    PROJECT_CONTEXT rv;
+    wxFileName pro( filename );
+    wxFileName brdName ( filename );
+    pro.SetExt( ProjectFileExtension );
+    brdName.SetExt( KiCadPcbFileExtension );
+
+    g_settingsManager.LoadProject( pro.GetFullPath() );
+
+    rv.project = &g_settingsManager.Prj();
+    rv.board.reset( KI_TEST::ReadBoardFromFileOrStream( (const char *) brdName.GetFullPath().c_str() ).release() );
+    rv.board->SetProject( rv.project );
+
+    return rv;
+}
+
+
 int main( int argc, char *argv[] )
 {
     PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance();
@@ -166,9 +196,11 @@ int main( int argc, char *argv[] )
         return -1;
     }
 
-    auto brd =  KI_TEST::ReadBoardFromFileOrStream( argv[1] );
+    PROJECT_CONTEXT project = loadKicadProject( argv[1] );
 
-    test::DRC_ENGINE drcEngine( brd.get(), &brd->GetDesignSettings() );
+
+
+    test::DRC_ENGINE drcEngine( project.board.get(), &project.board->GetDesignSettings() );
 
     CONSOLE_LOG consoleLog;
 

qa/drc_proto/drc_test_provider_hole_clearance.cpp

@@ -237,7 +237,7 @@ bool test::DRC_TEST_PROVIDER_HOLE_CLEARANCE::doPadToPadHoleDrc(  D_PAD* aRefPad,
 
 //        drc_dbg(10," chk2 against -> %p ds %d %d\n", pad, pad->GetDrillSize().x, aRefPad->GetDrillSize().x );
 
-        drc_dbg(1," chk1 against -> %p x0 %d x2 %d\n", pad, pad->GetDrillSize().x, aRefPad->GetDrillSize().x );
+        drc_dbg(10," chk1 against -> %p x0 %d x2 %d\n", pad, pad->GetDrillSize().x, aRefPad->GetDrillSize().x );
 
         // No problem if pads which are on copper layers are on different copper layers,
         // (pads can be only on a technical layer, to build complex pads)
@@ -262,7 +262,7 @@ bool test::DRC_TEST_PROVIDER_HOLE_CLEARANCE::doPadToPadHoleDrc(  D_PAD* aRefPad,
                     continue;
             }
 
-            drc_dbg(1," chk3 against -> %p x0 %d x2 %d\n", pad, pad->GetDrillSize().x, aRefPad->GetDrillSize().x );
+            drc_dbg(10," chk3 against -> %p x0 %d x2 %d\n", pad, pad->GetDrillSize().x, aRefPad->GetDrillSize().x );
 
             /* Here, we must test clearance between holes and pads
              * pad size and shape is adjusted to pad drill size and shape
@@ -275,7 +275,7 @@ bool test::DRC_TEST_PROVIDER_HOLE_CLEARANCE::doPadToPadHoleDrc(  D_PAD* aRefPad,
                 auto minClearance = constraint.GetValue().Min();
                 int actual;
 
-                drc_dbg(1,"check pad %p rule '%s' cl %d\n", pad, constraint.GetParentRule()->GetName(), minClearance );
+                drc_dbg(10,"check pad %p rule '%s' cl %d\n", pad, constraint.GetParentRule()->GetName(), minClearance );
 
                 accountCheck( constraint.GetParentRule() );
 
@@ -310,7 +310,7 @@ bool test::DRC_TEST_PROVIDER_HOLE_CLEARANCE::doPadToPadHoleDrc(  D_PAD* aRefPad,
 
                 accountCheck( constraint.GetParentRule() );
 
-                drc_dbg(1,"check pad %p rule '%s' cl %d\n", aRefPad, constraint.GetParentRule()->GetName(), minClearance );
+                drc_dbg(10,"check pad %p rule '%s' cl %d\n", aRefPad, constraint.GetParentRule()->GetName(), minClearance );
 
                 auto padShape = pad->GetEffectiveShape();
                 if( padShape->Collide( aRefPad->GetEffectiveHoleShape(), minClearance, &actual ) )

qa/drc_proto/drc_test_provider_hole_size.cpp

@@ -92,6 +92,8 @@ bool test::DRC_TEST_PROVIDER_HOLE_SIZE::Run()
 {
     ReportStage( ( "Testing pad holes" ), 0, 2 );
 
+    m_board = m_drcEngine->GetBoard();
+
     for( auto module : m_board->Modules() )
     {
         for( auto pad : module->Pads() )