Update demos

This commit is contained in:
jean-pierre charras 2020-10-25 18:50:20 +01:00
parent 09ade9fe51
commit fd62c42ded
18 changed files with 28860 additions and 8851 deletions

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@ -1,34 +1,37 @@
(module "RV2X4" (layer F.Cu) (tedit 5D822C01)
(module "RV2X4" (layer "F.Cu") (tedit 5F95B8F7)
(descr "Resistance variable / Potentiometre")
(tags "R")
(fp_text reference "RV2X4" (at 2.54 -2.54) (layer F.SilkS)
(attr through_hole)
(fp_text reference "RV2X4" (at 2.54 -2.54) (layer "F.SilkS")
(effects (font (size 1.397 1.27) (thickness 0.2032)))
(tstamp 9884b2ba-ffde-4027-9db5-9614101bd8f5)
)
(fp_text value "VAL***" (at 3.429 8.001) (layer F.Fab)
(fp_text value "VAL***" (at 3.429 8.001) (layer "F.Fab")
(effects (font (size 1.397 1.27) (thickness 0.2032)))
(tstamp 9bea7ee6-79aa-405c-ae07-cbad42c83963)
)
(fp_line (start -2.92 6.79) (end -2.92 -1.71) (layer F.CrtYd) (width 0.15))
(fp_line (start 9.33 6.79) (end -2.92 6.79) (layer F.CrtYd) (width 0.15))
(fp_line (start 12.08 4.04) (end 9.33 6.79) (layer F.CrtYd) (width 0.15))
(fp_line (start 12.08 1.04) (end 12.08 4.04) (layer F.CrtYd) (width 0.15))
(fp_line (start 9.33 -1.71) (end 12.08 1.04) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.92 -1.71) (end 9.33 -1.71) (layer F.CrtYd) (width 0.15))
(fp_circle (center 6.35 2.54) (end 2.54 1.905) (layer F.SilkS) (width 0.3048))
(fp_line (start 2.54 3.048) (end 10.033 3.048) (layer F.SilkS) (width 0.3048))
(fp_line (start 2.54 2.032) (end 10.033 2.032) (layer F.SilkS) (width 0.3048))
(fp_line (start 6.731 6.35) (end 5.842 6.35) (layer F.SilkS) (width 0.3048))
(fp_line (start 5.842 -1.27) (end 6.985 -1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start -2.54 6.35) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start 8.89 6.35) (end -2.54 6.35) (layer F.SilkS) (width 0.3048))
(fp_line (start 11.43 3.81) (end 8.89 6.35) (layer F.SilkS) (width 0.3048))
(fp_line (start 11.43 1.27) (end 11.43 3.81) (layer F.SilkS) (width 0.3048))
(fp_line (start 8.89 -1.27) (end 11.43 1.27) (layer F.SilkS) (width 0.3048))
(fp_line (start -2.54 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.3048))
(pad "1" thru_hole circle (at 0 0) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask))
(pad "2" thru_hole circle (at 10.16 2.54) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask))
(pad "3" thru_hole circle (at 0 5.08) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask))
(fp_line (start 2.54 3.1) (end 9 3.1) (layer "F.SilkS") (width 0.3048) (tstamp 088b19af-3682-4613-b95f-ad5a463b8655))
(fp_line (start 8.89 -1.27) (end 11.43 1.27) (layer "F.SilkS") (width 0.3048) (tstamp 2cd0110b-3bf6-442f-bbcf-29535a7efca6))
(fp_line (start 2.54 2.032) (end 9 2.032) (layer "F.SilkS") (width 0.3048) (tstamp 2d8d7e0f-48ec-4bb1-9bc4-0a7d08b17582))
(fp_line (start 6.731 6.35) (end 5.842 6.35) (layer "F.SilkS") (width 0.3048) (tstamp 40312281-462c-45b3-9604-0289bb05eb4a))
(fp_line (start -2.54 6.35) (end -2.54 -1.27) (layer "F.SilkS") (width 0.3048) (tstamp 58e08177-e1ff-4f71-9e6a-32c7594a582d))
(fp_line (start 11.43 3.81) (end 8.89 6.35) (layer "F.SilkS") (width 0.3048) (tstamp 956ec177-c68d-490f-b88e-1ff57d07e81c))
(fp_line (start -2.54 -1.27) (end 8.89 -1.27) (layer "F.SilkS") (width 0.3048) (tstamp a250ea58-86cf-4011-9fd5-d09e138806a4))
(fp_line (start 8.89 6.35) (end -2.54 6.35) (layer "F.SilkS") (width 0.3048) (tstamp bd739ba4-4b04-4baf-9524-520bc30c3a3f))
(fp_line (start 5.842 -1.27) (end 6.985 -1.27) (layer "F.SilkS") (width 0.3048) (tstamp be32e781-837e-4542-9d7c-e912ac9c698f))
(fp_line (start 11.43 1.27) (end 11.43 3.81) (layer "F.SilkS") (width 0.3048) (tstamp e21bdf08-9bd7-48f5-a918-297f0b1476f1))
(fp_arc (start 6.35 2.55) (end 9.949999 1.250001) (angle -319.9) (layer "F.SilkS") (width 0.3) (tstamp 06b8c219-e711-4fa1-a0de-d9008eee714d))
(fp_line (start 12.08 4.04) (end 9.33 6.79) (layer "F.CrtYd") (width 0.15) (tstamp 1650488b-a01b-4f9e-9165-97e353859446))
(fp_line (start -2.92 6.79) (end -2.92 -1.71) (layer "F.CrtYd") (width 0.15) (tstamp 1c75880c-7a2c-47f9-9fbb-252881e2ee99))
(fp_line (start -2.92 -1.71) (end 9.33 -1.71) (layer "F.CrtYd") (width 0.15) (tstamp a8816542-dfa4-4638-97de-7480ce574fd8))
(fp_line (start 12.08 1.04) (end 12.08 4.04) (layer "F.CrtYd") (width 0.15) (tstamp ae956c75-2577-4012-82c2-3347927ece12))
(fp_line (start 9.33 6.79) (end -2.92 6.79) (layer "F.CrtYd") (width 0.15) (tstamp d96c5f81-3442-4da6-a23d-bd74b4b05415))
(fp_line (start 9.33 -1.71) (end 12.08 1.04) (layer "F.CrtYd") (width 0.15) (tstamp ec4a4a4b-d40b-4ebf-8da9-f235591218fd))
(pad "1" thru_hole circle (at 0 0) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask) (tstamp 107f61c3-584e-4e0e-8f69-d7703c4d9199))
(pad "2" thru_hole circle (at 10.16 2.54) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask) (tstamp 48ced4d2-445c-4f16-9395-99cc12211a67))
(pad "3" thru_hole circle (at 0 5.08) (size 2.032 2.032) (drill 1.27) (layers *.Cu *.Mask) (tstamp 9bcc53f0-5389-4660-8392-70ea55fb055f))
(model "Discret.3dshapes/RV2X4.wrl"
(at (xyz 0 0 0))
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 24C16
#
DEF 24C16 U 0 30 Y Y 1 F N
F0 "U" 150 350 60 H V C CNN
F1 "24C16" 200 -350 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS 24C512
DRAW
S -400 -300 400 300 1 1 0 N
X GND 4 0 -500 200 U 60 60 0 0 W
X VCC 8 0 500 200 D 60 60 0 0 W
X A0 1 -700 200 300 R 60 60 1 1 I
X A1 2 -700 100 300 R 60 60 1 1 I
X A2 3 -700 0 300 R 60 60 1 1 I
X SDA 5 700 -200 300 L 60 60 1 1 B
X SCL 6 700 -100 300 L 60 60 1 1 I
X WP 7 700 100 300 L 60 60 1 1 I
ENDDRAW
ENDDEF
#
# 74LS125
#
DEF 74LS125 U 0 10 Y Y 4 F N
F0 "U" 200 150 50 H V C CNN
F1 "74LS125" 300 -100 50 H V C CNN
F2 "" 100 50 10 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LVC125
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f
X VCC 14 -50 200 100 D 30 20 0 0 W
X GND 7 -50 -200 100 U 20 20 0 0 W
X ~ 1 100 -200 175 U 50 50 1 0 I I
X ~ 2 -300 0 150 R 50 50 1 0 I
X ~ 3 300 0 150 L 50 50 1 0 T
X ~ 4 100 -200 175 U 50 50 2 0 I I
X ~ 5 -300 0 150 R 50 50 2 0 I
X ~ 6 300 0 150 L 50 50 2 0 T
X ~ 10 100 -200 175 U 50 50 3 0 I I
X ~ 8 300 0 150 L 50 50 3 0 T
X ~ 9 -300 0 150 R 50 50 3 0 I
X ~ 11 300 0 150 L 50 50 4 0 T
X ~ 12 -300 0 150 R 50 50 4 0 I
X ~ 13 100 -200 175 U 50 50 4 0 I I
ENDDRAW
ENDDEF
#
# 7805
#
DEF 7805 U 0 30 Y Y 1 F N
F0 "U" 150 -196 60 H V C CNN
F1 "7805" 0 200 60 H V C CNN
F2 "" 50 -296 15 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LM7805 LM7812 78L05
DRAW
S -200 -150 200 150 0 1 0 N
X VI 1 -400 50 200 R 40 40 1 1 I
X GND 2 0 -250 100 U 30 40 1 1 I
X VO 3 400 50 200 L 40 40 1 1 w
ENDDRAW
ENDDEF
#
# BC237
#
DEF BC237 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 50 H V R CNN
F1 "BC237" 0 150 50 H V R CNN
F2 "Package_TO_SOT_THT:TO-92" -100 -200 15 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
P 3 0 1 10 0 75 0 -75 0 -75 N
P 3 0 1 0 50 -50 0 0 0 0 N
P 3 0 1 0 90 -90 100 -100 100 -100 N
P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
X C 1 100 200 100 D 40 40 1 1 P
X B 2 -200 0 200 R 40 40 1 1 I
X E 3 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# BC307
#
DEF BC307 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 60 H V R CNN
F1 "BC307" 0 150 60 H V R CNN
F2 "Package_TO_SOT_THT:TO-92" -100 -200 15 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
P 3 0 1 10 0 75 0 -75 0 -75 F
P 3 0 1 0 25 -25 0 0 0 0 N
P 3 0 1 0 100 -100 65 -65 65 -65 N
P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
X C 1 100 200 100 D 40 40 1 1 P
X B 2 -200 0 200 R 40 40 1 1 I
X E 3 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_1
#
DEF CONN_1 P 0 30 N N 1 F N
F0 "P" 80 0 40 H V L CNN
F1 "CONN_1" 0 55 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 0 31 0 1 0 N
P 2 0 1 0 -30 0 -50 0 N
X 1 ~ -150 0 100 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# CONN_2
#
DEF CONN_2 P 0 40 Y N 1 F N
F0 "P" -50 0 40 V V C CNN
F1 "CONN_2" 50 0 40 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -100 150 100 -150 0 1 0 N
X P1 1 -350 100 250 R 60 60 1 1 P I
X PM 2 -350 -100 250 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S -70 90 -30 90 0 1 0 N
S -50 70 -50 110 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# D
#
DEF D D 0 0 Y Y 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 30 30 1 1 P
X A 2 150 0 100 L 30 30 1 1 P
ENDDRAW
ENDDEF
#
# DB9
#
DEF DB9 J 0 40 Y N 1 F N
F0 "J" 0 550 70 H V C CNN
F1 "DB9" 0 -550 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
DB9*
$ENDFPLIST
DRAW
C -70 -400 30 0 1 0 N
C -70 -200 30 0 1 0 N
C -70 0 30 0 1 0 N
C -70 200 30 0 1 0 N
C -70 400 30 0 1 0 N
C 50 -300 30 0 1 0 N
C 50 -100 30 0 1 0 N
C 50 100 30 0 1 0 N
C 50 300 30 0 1 0 N
P 2 0 1 8 -150 -460 -150 460 N
P 2 0 1 8 -150 -459 -140 -470 N
P 2 0 1 0 -150 -400 -100 -400 N
P 2 0 1 0 -150 -300 20 -300 N
P 2 0 1 0 -150 -200 -100 -200 N
P 2 0 1 0 -150 -100 20 -100 N
P 2 0 1 0 -150 0 -100 0 N
P 2 0 1 0 -150 100 20 100 N
P 2 0 1 0 -150 200 -100 200 N
P 2 0 1 0 -150 300 20 300 N
P 2 0 1 0 -150 400 -100 400 N
P 2 0 1 8 -140 -470 -110 -490 N
P 2 0 1 8 -140 470 -150 460 N
P 2 0 1 8 -140 470 -100 490 N
P 2 0 1 8 -110 -490 -50 -490 N
P 2 0 1 8 -100 490 -70 490 N
P 2 0 1 8 129 390 -70 490 N
P 2 0 1 8 129 390 150 370 N
P 2 0 1 8 140 -409 -50 -490 N
P 2 0 1 8 150 -390 140 -409 N
P 2 0 1 8 150 370 150 -390 N
X 1 1 -450 -400 300 R 60 60 1 1 P
X 2 2 -450 -200 300 R 60 60 1 1 P
X 3 3 -450 0 300 R 60 60 1 1 P
X 4 4 -450 200 300 R 60 60 1 1 P
X 5 5 -450 400 300 R 60 60 1 1 P
X P6 6 -450 -300 300 R 60 60 1 1 P
X P7 7 -450 -100 300 R 60 60 1 1 P
X P8 8 -450 100 300 R 60 60 1 1 P
X P9 9 -450 300 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# D_Schottky
#
DEF D_Schottky D 0 0 Y Y 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "D_Schottky" 0 -100 50 H V C CNN
F2 "" -100 0 10 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
D-Pak_TO252AA
Diode_*
*SingleDiode
*SingleDiode*
*_Diode_*
$ENDFPLIST
DRAW
P 3 0 1 0 50 50 -50 0 50 -50 F
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 0 30 H I C CNN
F1 "GND" 0 -70 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
X GND 1 0 0 0 U 30 30 1 1 W N
ENDDRAW
ENDDEF
#
# INDUCTOR
#
DEF INDUCTOR L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "INDUCTOR" 100 0 50 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 0 -150 50 -889 889 0 1 0 N 1 -199 1 -100
A 0 -49 51 -889 889 0 1 0 N 1 -99 1 2
A 0 51 51 -889 889 0 1 0 N 1 1 1 102
A 0 148 48 -889 889 0 1 0 N 1 101 1 196
X 1 1 0 300 100 D 70 70 1 1 P
X 2 2 0 -300 100 U 70 70 1 1 P
ENDDRAW
ENDDEF
#
# JUMPER
#
DEF JUMPER JP 0 30 Y N 1 F N
F0 "JP" 0 150 50 H V C CNN
F1 "JUMPER" 0 -80 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 0 -26 125 1426 373 0 1 0 N -98 50 99 50
C -100 0 35 0 1 0 N
C 100 0 35 0 1 0 N
X 1 1 -300 0 165 R 60 60 0 1 P
X 2 2 300 0 165 L 60 60 0 1 P
ENDDRAW
ENDDEF
#
# LED
#
DEF LED D 0 40 Y N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "LED" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
LED-3MM
LED-5MM
LED-10MM
LED-0603
LED-0805
LED-1206
LEDV
$ENDFPLIST
DRAW
P 2 0 1 0 -50 50 -50 -50 N
P 3 0 1 0 -80 -25 -125 -65 -120 -40 N
P 3 0 1 0 -65 -40 -110 -80 -105 -55 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -200 0 150 R 40 40 1 1 P
X A 2 200 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# LT1372
#
DEF LT1372 U 0 30 Y Y 1 F N
F0 "U" 600 500 60 H V C CNN
F1 "LT1372" -500 500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LT1373
DRAW
S -700 -400 700 400 0 1 0 N
X Vc 1 250 -700 300 U 60 60 1 1 I
X FB+ 2 1000 -250 300 L 60 60 1 1 I
X FB- 3 -1000 250 300 R 60 60 1 1 P
X S/S 4 -1000 -250 300 R 60 60 1 1 P
X Vin 5 0 700 300 D 60 60 1 1 W
X GND_S 6 -150 -700 300 U 60 60 1 1 I
X GND 7 -300 -700 300 U 60 60 1 1 I
X Vsw 8 1000 250 300 L 60 60 1 1 I
ENDDRAW
ENDDEF
#
# MOUNTING_HOLE
#
DEF MOUNTING_HOLE P 0 30 N N 1 F N
F0 "P" 80 0 40 H V L CNN
F1 "MOUNTING_HOLE" 0 55 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
*Hole*
$ENDFPLIST
DRAW
C 0 0 31 0 1 0 N
ENDDRAW
ENDDEF
#
# PIC12C508A
#
DEF PIC12C508A U 0 40 Y Y 1 F N
F0 "U" 0 700 60 H V C CNN
F1 "PIC12C508A" 0 -650 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS PIC12C509A
DRAW
S 400 -600 -450 650 0 1 0 N
X VDD 1 -750 500 300 R 50 50 1 1 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 1 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 1 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 1 I
X GP2 5 700 -500 300 L 50 50 1 1 I
X GP1 6 700 -200 300 L 50 50 1 1 I
X GP0 7 700 200 300 L 50 50 1 1 I
X VSS 8 700 500 300 L 50 50 1 1 W
X VDD 1 -750 500 300 R 50 50 1 2 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 2 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 2 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 2 I
X GP2 5 700 -500 300 L 50 50 1 2 I
X GP1 6 700 -200 300 L 50 50 1 2 I
X GP0 7 700 200 300 L 50 50 1 2 I
X VSS 8 700 500 300 L 50 50 1 2 W
ENDDRAW
ENDDEF
#
# PIC16F54
#
DEF PIC16F54 U? 0 40 Y Y 1 F N
F0 "U?" 0 -750 60 H V C CNN
F1 "PIC16F54" 0 800 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -500 700 450 -700 0 1 0 N
X RA2 1 -800 600 300 R 50 50 1 1 B
X RB4 10 750 -600 300 L 50 50 1 1 B
X RB5 11 750 -450 300 L 50 50 1 1 B
X ICSPC/RB6 12 750 -300 300 L 50 50 1 1 B
X ICSPD/RB7 13 750 -150 300 L 50 50 1 1 B
X VDD 14 750 0 300 L 50 50 1 1 W
X OSC2/CLKO 15 750 150 300 L 50 50 1 1 O
X OSC1/CLKI 16 750 300 300 L 50 50 1 1 I
X RA0 17 750 450 300 L 50 50 1 1 B
X RA1 18 750 600 300 L 50 50 1 1 B
X RA3 2 -800 450 300 R 50 50 1 1 B
X T0ckl 3 -800 300 300 R 50 50 1 1 O
X MCLR 4 -800 150 300 R 50 50 1 1 I
X VSS 5 -800 0 300 R 50 50 1 1 W
X RB0 6 -800 -150 300 R 50 50 1 1 B
X RB1 7 -800 -300 300 R 50 50 1 1 B
X RB2 8 -800 -450 300 R 50 50 1 1 B
X RB3 9 -800 -600 300 R 50 50 1 1 B
X RA2 1 -800 600 300 R 50 50 1 2 B
X RB4 10 750 -600 300 L 50 50 1 2 B
X RB5 11 750 -450 300 L 50 50 1 2 B
X ICSPC/RB6 12 750 -300 300 L 50 50 1 2 B
X ICSPD/RB7 13 750 -150 300 L 50 50 1 2 B
X VDD 14 750 0 300 L 50 50 1 2 W
X OSC2/CLKO 15 750 150 300 L 50 50 1 2 O
X OSC1/CLKI 16 750 300 300 L 50 50 1 2 I
X RA0 17 750 450 300 L 50 50 1 2 B
X RA1 18 750 600 300 L 50 50 1 2 B
X RA3 2 -800 450 300 R 50 50 1 2 B
X T0ckl 3 -800 300 300 R 50 50 1 2 O
X MCLR 4 -800 150 300 R 50 50 1 2 I
X VSS 5 -800 0 300 R 50 50 1 2 W
X RB0 6 -800 -150 300 R 50 50 1 2 B
X RB1 7 -800 -300 300 R 50 50 1 2 B
X RB2 8 -800 -450 300 R 50 50 1 2 B
X RB3 9 -800 -600 300 R 50 50 1 2 B
ENDDRAW
ENDDEF
#
# POT
#
DEF POT RV 0 40 Y N 1 F N
F0 "RV" 0 -100 50 H V C CNN
F1 "POT" 0 0 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -150 50 150 -50 0 1 0 N
P 3 0 1 0 0 50 -20 70 20 70 F
X 1 1 -250 0 100 R 40 40 1 1 P
X 2 2 0 150 80 D 40 40 1 1 P
X 3 3 250 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 30 H I C CNN
F1 "PWR_FLAG" 0 180 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
X pwr 1 0 0 0 U 20 20 0 0 w
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 30 V V C CNN
F3 "" 0 0 30 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 60 60 1 1 P
X ~ 2 0 -150 50 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# SUPP28
#
DEF SUPP28 J 0 40 Y Y 1 F N
F0 "J" 0 100 70 H V C CNN
F1 "SUPP28" 0 -100 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -750 300 750 0 1 0 N
X 1 1 -600 650 300 R 60 60 1 1 P
X 10 10 -600 -250 300 R 60 60 1 1 P
X 11 11 -600 -350 300 R 60 60 1 1 P
X 12 12 -600 -450 300 R 60 60 1 1 P
X 13 13 -600 -550 300 R 60 60 1 1 P
X 14 14 -600 -650 300 R 60 60 1 1 P
X 15 15 600 -650 300 L 60 60 1 1 P
X 16 16 600 -550 300 L 60 60 1 1 P
X 17 17 600 -450 300 L 60 60 1 1 P
X 18 18 600 -350 300 L 60 60 1 1 P
X 19 19 600 -250 300 L 60 60 1 1 P
X 2 2 -600 550 300 R 60 60 1 1 P
X 20 20 600 -150 300 L 60 60 1 1 P
X 21 21 600 -50 300 L 60 60 1 1 P
X 22 22 600 50 300 L 60 60 1 1 P
X 23 23 600 150 300 L 60 60 1 1 P
X 24 24 600 250 300 L 60 60 1 1 P
X 25 25 600 350 300 L 60 60 1 1 P
X 26 26 600 450 300 L 60 60 1 1 P
X 27 27 600 550 300 L 60 60 1 1 P
X 28 28 600 650 300 L 60 60 1 1 P
X 3 3 -600 450 300 R 60 60 1 1 P
X 4 4 -600 350 300 R 60 60 1 1 P
X 5 5 -600 250 300 R 60 60 1 1 P
X 6 6 -600 150 300 R 60 60 1 1 P
X 7 7 -600 50 300 R 60 60 1 1 P
X 8 8 -600 -50 300 R 60 60 1 1 P
X 9 9 -600 -150 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# SUPP40
#
DEF SUPP40 P 0 40 Y Y 1 F N
F0 "P" 0 1100 70 H V C CNN
F1 "SUPP40" 0 -1100 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -1050 300 1050 0 1 0 N
X 1 1 -600 950 300 R 60 60 1 1 P
X 10 10 -600 50 300 R 60 60 1 1 P
X 11 11 -600 -50 300 R 60 60 1 1 P
X 12 12 -600 -150 300 R 60 60 1 1 P
X 13 13 -600 -250 300 R 60 60 1 1 P
X 14 14 -600 -350 300 R 60 60 1 1 P
X 15 15 -600 -450 300 R 60 60 1 1 P
X 16 16 -600 -550 300 R 60 60 1 1 P
X 17 17 -600 -650 300 R 60 60 1 1 P
X 18 18 -600 -750 300 R 60 60 1 1 P
X 19 19 -600 -850 300 R 60 60 1 1 P
X 2 2 -600 850 300 R 60 60 1 1 P
X 20 20 -600 -950 300 R 60 60 1 1 P
X 21 21 600 -950 300 L 60 60 1 1 P
X 22 22 600 -850 300 L 60 60 1 1 P
X 23 23 600 -750 300 L 60 60 1 1 P
X 24 24 600 -650 300 L 60 60 1 1 P
X 25 25 600 -550 300 L 60 60 1 1 P
X 26 26 600 -450 300 L 60 60 1 1 P
X 27 27 600 -350 300 L 60 60 1 1 P
X 28 28 600 -250 300 L 60 60 1 1 P
X 29 29 600 -150 300 L 60 60 1 1 P
X 3 3 -600 750 300 R 60 60 1 1 P
X 30 30 600 -50 300 L 60 60 1 1 P
X 31 31 600 50 300 L 60 60 1 1 P
X 32 32 600 150 300 L 60 60 1 1 P
X 33 33 600 250 300 L 60 60 1 1 P
X 34 34 600 350 300 L 60 60 1 1 P
X 35 35 600 450 300 L 60 60 1 1 P
X 36 36 600 550 300 L 60 60 1 1 P
X 37 37 600 650 300 L 60 60 1 1 P
X 38 38 600 750 300 L 60 60 1 1 P
X 39 39 600 850 300 L 60 60 1 1 P
X 4 4 -600 650 300 R 60 60 1 1 P
X 40 40 600 950 300 L 60 60 1 1 P
X 5 5 -600 550 300 R 60 60 1 1 P
X 6 6 -600 450 300 R 60 60 1 1 P
X 7 7 -600 350 300 R 60 60 1 1 P
X 8 8 -600 250 300 R 60 60 1 1 P
X 9 9 -600 150 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 30 H I C CNN
F1 "VCC" 0 100 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 50 20 0 1 0 N
P 3 0 1 0 0 0 0 30 0 30 N
X VCC 1 0 0 0 U 20 20 0 0 W N
ENDDRAW
ENDDEF
#
# VPP
#
DEF VPP #PWR 0 0 Y Y 1 F N
F0 "#PWR" 0 200 40 H I C CNN
F1 "VPP" 0 150 40 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 80 20 0 1 0 N
P 2 0 1 0 0 60 0 0 N
X VPP 1 0 0 0 U 40 40 0 0 W N
ENDDRAW
ENDDEF
#
#End Library

View File

@ -1,627 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# pic_programmer_schlib_24C16
#
DEF pic_programmer_schlib_24C16 U 0 30 Y Y 1 F N
F0 "U" 150 350 60 H V C CNN
F1 "pic_programmer_schlib_24C16" 200 -350 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS 24C512
DRAW
S -400 -300 400 300 1 1 0 N
X GND 4 0 -500 200 U 60 60 0 0 W
X VCC 8 0 500 200 D 60 60 0 0 W
X A0 1 -700 200 300 R 60 60 1 1 I
X A1 2 -700 100 300 R 60 60 1 1 I
X A2 3 -700 0 300 R 60 60 1 1 I
X SDA 5 700 -200 300 L 60 60 1 1 B
X SCL 6 700 -100 300 L 60 60 1 1 I
X WP 7 700 100 300 L 60 60 1 1 I
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_74LS125
#
DEF pic_programmer_schlib_74LS125 U 0 10 Y Y 4 F N
F0 "U" 200 150 50 H V C CNN
F1 "pic_programmer_schlib_74LS125" 300 -100 50 H V C CNN
F2 "" 100 50 10 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LVC125
$FPLIST
DIP?14*
$ENDFPLIST
DRAW
P 4 1 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 2 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 3 0 10 -150 150 -150 -150 150 0 -150 150 f
P 4 4 0 10 -150 150 -150 -150 150 0 -150 150 f
X VCC 14 -50 200 100 D 30 20 0 0 W
X GND 7 -50 -200 100 U 20 20 0 0 W
X ~ 1 100 -200 175 U 50 50 1 0 I I
X ~ 2 -300 0 150 R 50 50 1 0 I
X ~ 3 300 0 150 L 50 50 1 0 T
X ~ 4 100 -200 175 U 50 50 2 0 I I
X ~ 5 -300 0 150 R 50 50 2 0 I
X ~ 6 300 0 150 L 50 50 2 0 T
X ~ 10 100 -200 175 U 50 50 3 0 I I
X ~ 8 300 0 150 L 50 50 3 0 T
X ~ 9 -300 0 150 R 50 50 3 0 I
X ~ 11 300 0 150 L 50 50 4 0 T
X ~ 12 -300 0 150 R 50 50 4 0 I
X ~ 13 100 -200 175 U 50 50 4 0 I I
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_7805
#
DEF pic_programmer_schlib_7805 U 0 30 Y Y 1 F N
F0 "U" 150 -196 60 H V C CNN
F1 "pic_programmer_schlib_7805" 0 200 60 H V C CNN
F2 "" 50 -296 15 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LM7805 LM7812 78L05
DRAW
S -200 -150 200 150 0 1 0 N
X VI 1 -400 50 200 R 40 40 1 1 I
X GND 2 0 -250 100 U 30 40 1 1 I
X VO 3 400 50 200 L 40 40 1 1 w
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_BC237
#
DEF pic_programmer_schlib_BC237 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 50 H V R CNN
F1 "pic_programmer_schlib_BC237" 0 150 50 H V R CNN
F2 "Package_TO_SOT_THT:TO-92" -100 -200 15 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
P 3 0 1 10 0 75 0 -75 0 -75 N
P 3 0 1 0 50 -50 0 0 0 0 N
P 3 0 1 0 90 -90 100 -100 100 -100 N
P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F
X C 1 100 200 100 D 40 40 1 1 P
X B 2 -200 0 200 R 40 40 1 1 I
X E 3 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_BC307
#
DEF pic_programmer_schlib_BC307 Q 0 0 Y Y 1 F N
F0 "Q" 0 -150 60 H V R CNN
F1 "pic_programmer_schlib_BC307" 0 150 60 H V R CNN
F2 "Package_TO_SOT_THT:TO-92" -100 -200 15 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 100 100 N
P 3 0 1 10 0 75 0 -75 0 -75 F
P 3 0 1 0 25 -25 0 0 0 0 N
P 3 0 1 0 100 -100 65 -65 65 -65 N
P 5 0 1 0 25 -25 50 -75 75 -50 25 -25 25 -25 F
X C 1 100 200 100 D 40 40 1 1 P
X B 2 -200 0 200 R 40 40 1 1 I
X E 3 100 -200 100 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_C
#
DEF pic_programmer_schlib_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "pic_programmer_schlib_C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_CONN_2
#
DEF pic_programmer_schlib_CONN_2 P 0 40 Y N 1 F N
F0 "P" -50 0 40 V V C CNN
F1 "pic_programmer_schlib_CONN_2" 50 0 40 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -100 150 100 -150 0 1 0 N
X P1 1 -350 100 250 R 60 60 1 1 P I
X PM 2 -350 -100 250 R 60 60 1 1 P I
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_CP
#
DEF pic_programmer_schlib_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "pic_programmer_schlib_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
CP*
Elko*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S -70 90 -30 90 0 1 0 N
S -50 70 -50 110 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_D
#
DEF pic_programmer_schlib_D D 0 0 Y Y 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "pic_programmer_schlib_D" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
Diode_*
D-Pak_TO252AA
*SingleDiode
*_Diode_*
*SingleDiode*
$ENDFPLIST
DRAW
P 2 0 1 6 -50 50 -50 -50 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -150 0 100 R 30 30 1 1 P
X A 2 150 0 100 L 30 30 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_DB9
#
DEF pic_programmer_schlib_DB9 J 0 40 Y N 1 F N
F0 "J" 0 550 70 H V C CNN
F1 "pic_programmer_schlib_DB9" 0 -550 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
DB9*
$ENDFPLIST
DRAW
C -70 -400 30 0 1 0 N
C -70 -200 30 0 1 0 N
C -70 0 30 0 1 0 N
C -70 200 30 0 1 0 N
C -70 400 30 0 1 0 N
C 50 -300 30 0 1 0 N
C 50 -100 30 0 1 0 N
C 50 100 30 0 1 0 N
C 50 300 30 0 1 0 N
P 2 0 1 8 -150 -460 -150 460 N
P 2 0 1 8 -150 -459 -140 -470 N
P 2 0 1 0 -150 -400 -100 -400 N
P 2 0 1 0 -150 -300 20 -300 N
P 2 0 1 0 -150 -200 -100 -200 N
P 2 0 1 0 -150 -100 20 -100 N
P 2 0 1 0 -150 0 -100 0 N
P 2 0 1 0 -150 100 20 100 N
P 2 0 1 0 -150 200 -100 200 N
P 2 0 1 0 -150 300 20 300 N
P 2 0 1 0 -150 400 -100 400 N
P 2 0 1 8 -140 -470 -110 -490 N
P 2 0 1 8 -140 470 -150 460 N
P 2 0 1 8 -140 470 -100 490 N
P 2 0 1 8 -110 -490 -50 -490 N
P 2 0 1 8 -100 490 -70 490 N
P 2 0 1 8 129 390 -70 490 N
P 2 0 1 8 129 390 150 370 N
P 2 0 1 8 140 -409 -50 -490 N
P 2 0 1 8 150 -390 140 -409 N
P 2 0 1 8 150 370 150 -390 N
X 1 1 -450 -400 300 R 60 60 1 1 P
X 2 2 -450 -200 300 R 60 60 1 1 P
X 3 3 -450 0 300 R 60 60 1 1 P
X 4 4 -450 200 300 R 60 60 1 1 P
X 5 5 -450 400 300 R 60 60 1 1 P
X P6 6 -450 -300 300 R 60 60 1 1 P
X P7 7 -450 -100 300 R 60 60 1 1 P
X P8 8 -450 100 300 R 60 60 1 1 P
X P9 9 -450 300 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_D_Schottky
#
DEF pic_programmer_schlib_D_Schottky D 0 0 Y Y 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "pic_programmer_schlib_D_Schottky" 0 -100 50 H V C CNN
F2 "" -100 0 10 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
D-Pak_TO252AA
Diode_*
*SingleDiode
*SingleDiode*
*_Diode_*
$ENDFPLIST
DRAW
P 3 0 1 0 50 50 -50 0 50 -50 F
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_GND
#
DEF pic_programmer_schlib_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 0 30 H I C CNN
F1 "pic_programmer_schlib_GND" 0 -70 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
X GND 1 0 0 0 U 30 30 1 1 W N
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_INDUCTOR
#
DEF pic_programmer_schlib_INDUCTOR L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "pic_programmer_schlib_INDUCTOR" 100 0 50 V V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 0 -150 50 -889 889 0 1 0 N 1 -199 1 -100
A 0 -49 51 -889 889 0 1 0 N 1 -99 1 2
A 0 51 51 -889 889 0 1 0 N 1 1 1 102
A 0 148 48 -889 889 0 1 0 N 1 101 1 196
X 1 1 0 300 100 D 70 70 1 1 P
X 2 2 0 -300 100 U 70 70 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_JUMPER
#
DEF pic_programmer_schlib_JUMPER JP 0 30 Y N 1 F N
F0 "JP" 0 150 50 H V C CNN
F1 "pic_programmer_schlib_JUMPER" 0 -80 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 0 -26 125 1426 373 0 1 0 N -98 50 99 50
C -100 0 35 0 1 0 N
C 100 0 35 0 1 0 N
X 1 1 -300 0 165 R 60 60 0 1 P
X 2 2 300 0 165 L 60 60 0 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_LED
#
DEF pic_programmer_schlib_LED D 0 40 Y N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "pic_programmer_schlib_LED" 0 -100 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
LED-3MM
LED-5MM
LED-10MM
LED-0603
LED-0805
LED-1206
LEDV
$ENDFPLIST
DRAW
P 2 0 1 0 -50 50 -50 -50 N
P 3 0 1 0 -80 -25 -125 -65 -120 -40 N
P 3 0 1 0 -65 -40 -110 -80 -105 -55 N
P 3 0 1 0 50 50 -50 0 50 -50 F
X K 1 -200 0 150 R 40 40 1 1 P
X A 2 200 0 150 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_LT1373
#
DEF pic_programmer_schlib_LT1373 U 0 30 Y Y 1 F N
F0 "U" 600 500 60 H V C CNN
F1 "pic_programmer_schlib_LT1373" -500 500 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS LT1373
DRAW
S -700 -400 700 400 0 1 0 N
X Vc 1 250 -700 300 U 60 60 1 1 I
X FB+ 2 1000 -250 300 L 60 60 1 1 I
X FB- 3 -1000 250 300 R 60 60 1 1 P
X S/S 4 -1000 -250 300 R 60 60 1 1 P
X Vin 5 0 700 300 D 60 60 1 1 W
X GND_S 6 -150 -700 300 U 60 60 1 1 I
X GND 7 -300 -700 300 U 60 60 1 1 I
X Vsw 8 1000 250 300 L 60 60 1 1 I
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_MOUNTING_HOLE
#
DEF pic_programmer_schlib_MOUNTING_HOLE P 0 30 N N 1 F N
F0 "P" 80 0 40 H V L CNN
F1 "pic_programmer_schlib_MOUNTING_HOLE" 0 55 30 H I C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
*Hole*
$ENDFPLIST
DRAW
C 0 0 31 0 1 0 N
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_PIC12C508A
#
DEF pic_programmer_schlib_PIC12C508A U 0 40 Y Y 1 F N
F0 "U" 0 700 60 H V C CNN
F1 "pic_programmer_schlib_PIC12C508A" 0 -650 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS PIC12C509A
DRAW
S 400 -600 -450 650 0 1 0 N
X VDD 1 -750 500 300 R 50 50 1 1 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 1 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 1 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 1 I
X GP2 5 700 -500 300 L 50 50 1 1 I
X GP1 6 700 -200 300 L 50 50 1 1 I
X GP0 7 700 200 300 L 50 50 1 1 I
X VSS 8 700 500 300 L 50 50 1 1 W
X VDD 1 -750 500 300 R 50 50 1 2 W
X GP5/OSC1 2 -750 200 300 R 50 50 1 2 I
X GP4/OSC2 3 -750 -200 300 R 50 50 1 2 I
X GP3/MCLR 4 -750 -500 300 R 50 50 1 2 I
X GP2 5 700 -500 300 L 50 50 1 2 I
X GP1 6 700 -200 300 L 50 50 1 2 I
X GP0 7 700 200 300 L 50 50 1 2 I
X VSS 8 700 500 300 L 50 50 1 2 W
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_PIC16F54
#
DEF pic_programmer_schlib_PIC16F54 U? 0 40 Y Y 1 F N
F0 "U?" 0 -750 60 H V C CNN
F1 "pic_programmer_schlib_PIC16F54" 0 800 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -500 700 450 -700 0 1 0 N
X RA2 1 -800 600 300 R 50 50 1 1 B
X RB4 10 750 -600 300 L 50 50 1 1 B
X RB5 11 750 -450 300 L 50 50 1 1 B
X ICSPC/RB6 12 750 -300 300 L 50 50 1 1 B
X ICSPD/RB7 13 750 -150 300 L 50 50 1 1 B
X VDD 14 750 0 300 L 50 50 1 1 W
X OSC2/CLKO 15 750 150 300 L 50 50 1 1 O
X OSC1/CLKI 16 750 300 300 L 50 50 1 1 I
X RA0 17 750 450 300 L 50 50 1 1 B
X RA1 18 750 600 300 L 50 50 1 1 B
X RA3 2 -800 450 300 R 50 50 1 1 B
X T0ckl 3 -800 300 300 R 50 50 1 1 O
X MCLR 4 -800 150 300 R 50 50 1 1 I
X VSS 5 -800 0 300 R 50 50 1 1 W
X RB0 6 -800 -150 300 R 50 50 1 1 B
X RB1 7 -800 -300 300 R 50 50 1 1 B
X RB2 8 -800 -450 300 R 50 50 1 1 B
X RB3 9 -800 -600 300 R 50 50 1 1 B
X RA2 1 -800 600 300 R 50 50 1 2 B
X RB4 10 750 -600 300 L 50 50 1 2 B
X RB5 11 750 -450 300 L 50 50 1 2 B
X ICSPC/RB6 12 750 -300 300 L 50 50 1 2 B
X ICSPD/RB7 13 750 -150 300 L 50 50 1 2 B
X VDD 14 750 0 300 L 50 50 1 2 W
X OSC2/CLKO 15 750 150 300 L 50 50 1 2 O
X OSC1/CLKI 16 750 300 300 L 50 50 1 2 I
X RA0 17 750 450 300 L 50 50 1 2 B
X RA1 18 750 600 300 L 50 50 1 2 B
X RA3 2 -800 450 300 R 50 50 1 2 B
X T0ckl 3 -800 300 300 R 50 50 1 2 O
X MCLR 4 -800 150 300 R 50 50 1 2 I
X VSS 5 -800 0 300 R 50 50 1 2 W
X RB0 6 -800 -150 300 R 50 50 1 2 B
X RB1 7 -800 -300 300 R 50 50 1 2 B
X RB2 8 -800 -450 300 R 50 50 1 2 B
X RB3 9 -800 -600 300 R 50 50 1 2 B
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_POT
#
DEF pic_programmer_schlib_POT RV 0 40 Y N 1 F N
F0 "RV" 0 -100 50 H V C CNN
F1 "pic_programmer_schlib_POT" 0 0 50 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -150 50 150 -50 0 1 0 N
P 3 0 1 0 0 50 -20 70 20 70 F
X 1 1 -250 0 100 R 40 40 1 1 P
X 2 2 0 150 80 D 40 40 1 1 P
X 3 3 250 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_PWR_FLAG
#
DEF pic_programmer_schlib_PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 30 H I C CNN
F1 "pic_programmer_schlib_PWR_FLAG" 0 180 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
X pwr 1 0 0 0 U 20 20 0 0 w
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_R
#
DEF pic_programmer_schlib_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "pic_programmer_schlib_R" 0 0 50 V V C CNN
F2 "" -70 0 30 V V C CNN
F3 "" 0 0 30 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 60 60 1 1 P
X ~ 2 0 -150 50 U 60 60 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_SUPP28
#
DEF pic_programmer_schlib_SUPP28 J 0 40 Y Y 1 F N
F0 "J" 0 100 70 H V C CNN
F1 "pic_programmer_schlib_SUPP28" 0 -100 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -750 300 750 0 1 0 N
X 1 1 -600 650 300 R 60 60 1 1 P
X 10 10 -600 -250 300 R 60 60 1 1 P
X 11 11 -600 -350 300 R 60 60 1 1 P
X 12 12 -600 -450 300 R 60 60 1 1 P
X 13 13 -600 -550 300 R 60 60 1 1 P
X 14 14 -600 -650 300 R 60 60 1 1 P
X 15 15 600 -650 300 L 60 60 1 1 P
X 16 16 600 -550 300 L 60 60 1 1 P
X 17 17 600 -450 300 L 60 60 1 1 P
X 18 18 600 -350 300 L 60 60 1 1 P
X 19 19 600 -250 300 L 60 60 1 1 P
X 2 2 -600 550 300 R 60 60 1 1 P
X 20 20 600 -150 300 L 60 60 1 1 P
X 21 21 600 -50 300 L 60 60 1 1 P
X 22 22 600 50 300 L 60 60 1 1 P
X 23 23 600 150 300 L 60 60 1 1 P
X 24 24 600 250 300 L 60 60 1 1 P
X 25 25 600 350 300 L 60 60 1 1 P
X 26 26 600 450 300 L 60 60 1 1 P
X 27 27 600 550 300 L 60 60 1 1 P
X 28 28 600 650 300 L 60 60 1 1 P
X 3 3 -600 450 300 R 60 60 1 1 P
X 4 4 -600 350 300 R 60 60 1 1 P
X 5 5 -600 250 300 R 60 60 1 1 P
X 6 6 -600 150 300 R 60 60 1 1 P
X 7 7 -600 50 300 R 60 60 1 1 P
X 8 8 -600 -50 300 R 60 60 1 1 P
X 9 9 -600 -150 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_SUPP40
#
DEF pic_programmer_schlib_SUPP40 P 0 40 Y Y 1 F N
F0 "P" 0 1100 70 H V C CNN
F1 "pic_programmer_schlib_SUPP40" 0 -1100 70 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S -300 -1050 300 1050 0 1 0 N
X 1 1 -600 950 300 R 60 60 1 1 P
X 10 10 -600 50 300 R 60 60 1 1 P
X 11 11 -600 -50 300 R 60 60 1 1 P
X 12 12 -600 -150 300 R 60 60 1 1 P
X 13 13 -600 -250 300 R 60 60 1 1 P
X 14 14 -600 -350 300 R 60 60 1 1 P
X 15 15 -600 -450 300 R 60 60 1 1 P
X 16 16 -600 -550 300 R 60 60 1 1 P
X 17 17 -600 -650 300 R 60 60 1 1 P
X 18 18 -600 -750 300 R 60 60 1 1 P
X 19 19 -600 -850 300 R 60 60 1 1 P
X 2 2 -600 850 300 R 60 60 1 1 P
X 20 20 -600 -950 300 R 60 60 1 1 P
X 21 21 600 -950 300 L 60 60 1 1 P
X 22 22 600 -850 300 L 60 60 1 1 P
X 23 23 600 -750 300 L 60 60 1 1 P
X 24 24 600 -650 300 L 60 60 1 1 P
X 25 25 600 -550 300 L 60 60 1 1 P
X 26 26 600 -450 300 L 60 60 1 1 P
X 27 27 600 -350 300 L 60 60 1 1 P
X 28 28 600 -250 300 L 60 60 1 1 P
X 29 29 600 -150 300 L 60 60 1 1 P
X 3 3 -600 750 300 R 60 60 1 1 P
X 30 30 600 -50 300 L 60 60 1 1 P
X 31 31 600 50 300 L 60 60 1 1 P
X 32 32 600 150 300 L 60 60 1 1 P
X 33 33 600 250 300 L 60 60 1 1 P
X 34 34 600 350 300 L 60 60 1 1 P
X 35 35 600 450 300 L 60 60 1 1 P
X 36 36 600 550 300 L 60 60 1 1 P
X 37 37 600 650 300 L 60 60 1 1 P
X 38 38 600 750 300 L 60 60 1 1 P
X 39 39 600 850 300 L 60 60 1 1 P
X 4 4 -600 650 300 R 60 60 1 1 P
X 40 40 600 950 300 L 60 60 1 1 P
X 5 5 -600 550 300 R 60 60 1 1 P
X 6 6 -600 450 300 R 60 60 1 1 P
X 7 7 -600 350 300 R 60 60 1 1 P
X 8 8 -600 250 300 R 60 60 1 1 P
X 9 9 -600 150 300 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_VCC
#
DEF pic_programmer_schlib_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 30 H I C CNN
F1 "pic_programmer_schlib_VCC" 0 100 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 50 20 0 1 0 N
P 3 0 1 0 0 0 0 30 0 30 N
X VCC 1 0 0 0 U 20 20 0 0 W N
ENDDRAW
ENDDEF
#
# pic_programmer_schlib_VPP
#
DEF pic_programmer_schlib_VPP #PWR 0 0 Y Y 1 F N
F0 "#PWR" 0 200 40 H I C CNN
F1 "pic_programmer_schlib_VPP" 0 150 40 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 80 20 0 1 0 N
P 2 0 1 0 0 60 0 0 N
X VPP 1 0 0 0 U 40 40 0 0 W N
ENDDRAW
ENDDEF
#
#End Library

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@ -0,0 +1,426 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.381,
"copper_line_width": 0.381,
"copper_text_italic": false,
"copper_text_size_h": 1.524,
"copper_text_size_v": 2.032,
"copper_text_thickness": 0.30479999999999996,
"copper_text_upright": true,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 1,
"dimension_units": 0,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": true,
"pads": {
"drill": 0.75,
"height": 1.3,
"width": 1.3
},
"silk_line_width": 0.381,
"silk_text_italic": false,
"silk_text_size_h": 1.524,
"silk_text_size_v": 1.524,
"silk_text_thickness": 0.30479999999999996,
"silk_text_upright": true,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_too_small": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"keepout": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_too_small": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"via_hole_larger_than_pad": "error",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.01,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.127,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.5,
"min_track_width": 0.25,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.8999999999999999,
"solder_mask_clearance": 0.09999999999999999,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": 0.0
},
"track_widths": [
0.5,
0.4,
0.5
],
"via_dimensions": [
{
"diameter": 1.6,
"drill": 0.6
}
],
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "error",
"no_connect_dangling": "error",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"legacy": {
"common": {
"NetDir": ""
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "pic_programmer.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.25,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.25,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"via_diameter": 1.6,
"via_drill": 0.6,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.28,
"diff_pair_gap": 0.28,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.28,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "POWER",
"nets": [
"GND",
"VCC"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.8,
"via_diameter": 1.6,
"via_drill": 0.6,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "pic_programmer.net",
"specctra_dsn": "",
"step": "pic_programmer.step",
"vmrl": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"72214582-898a-4d36-886b-c861eef43fbe",
""
],
[
"00000000-0000-0000-0000-00004804a5e2",
"pic_sockets"
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load Diff

View File

@ -1,261 +0,0 @@
update=15/04/2020 15:22:14
last_client=pcbnew
[common]
NetDir=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[eeschema]
version=1
LibDir=
[ModEditFrame]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=pic_programmer.net
LastSTEPExportPath=pic_programmer.step
LastIDFExportPath=
LastVRMLExportPath=
LastSpecctraDSNExportPath=
LastGenCADExportPath=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
MinTrackWidth=0.25
MinViaDiameter=0.8999999999999999
MinViaDrill=0.5
MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127
MinHoleToHole=0.25
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
CopperEdgeClearance=0.01
TrackWidth1=0.5
TrackWidth2=0.4
TrackWidth3=0.5
ViaDiameter1=1.6
ViaDrill1=0.6
dPairWidth1=0.25
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.381
SilkTextSizeV=1.524
SilkTextSizeH=1.524
SilkTextSizeThickness=0.3048
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.381
CopperTextSizeV=2.032
CopperTextSizeH=1.524
CopperTextThickness=0.3048
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.381
CourtyardLineWidth=0.05
OthersLineWidth=0.09999999999999999
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
DimensionUnits=0
DimensionPrecision=1
SolderMaskClearance=0.09999999999999999
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=top_layer
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=bottom_layer
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.25
TrackWidth=0.5
ViaDiameter=1.6
ViaDrill=0.6
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.25
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=POWER
Clearance=0.28
TrackWidth=0.8
ViaDiameter=1.6
ViaDrill=0.6
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.28
dPairGap=0.28
dPairViaGap=0.25

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -1,505 +0,0 @@
EESchema Schematic File Version 5
LIBS:pic_programmer-cache
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 2
Title "JDM - COM84 PIC Programmer with 13V DC/DC converter"
Date "Sun 22 Mar 2015"
Rev "3"
Comp "KiCad"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
Comment5 ""
Comment6 ""
Comment7 ""
Comment8 ""
Comment9 ""
$EndDescr
Wire Wire Line
3300 6600 3300 6500
Wire Wire Line
2100 2400 3000 2400
Wire Wire Line
9200 2000 10100 2000
Wire Wire Line
9200 1900 10000 1900
Wire Wire Line
7100 1900 8000 1900
Connection ~ 2800 1200
Wire Wire Line
2800 1200 3000 1200
Connection ~ 2800 1300
Wire Wire Line
2800 1100 2800 1200
Wire Wire Line
2800 1100 3000 1100
Wire Wire Line
3000 1300 2800 1300
Wire Wire Line
4400 1500 5300 1500
Wire Wire Line
4400 1400 5400 1400
Wire Wire Line
10100 4000 9200 4000
Wire Wire Line
10000 3900 9200 3900
Wire Wire Line
7100 3900 8000 3900
Wire Wire Line
2950 4600 2750 4600
Wire Wire Line
5400 4900 4500 4900
Wire Wire Line
5300 4750 4500 4750
Wire Wire Line
2200 4450 2950 4450
Wire Wire Line
5400 3100 4450 3100
Wire Wire Line
5300 2700 4450 2700
Wire Wire Line
3000 3400 2200 3400
Wire Wire Line
2750 4600 2750 4650
Wire Wire Line
5500 4600 4500 4600
Wire Wire Line
10200 2700 9200 2700
Wire Wire Line
10200 4700 9200 4700
Wire Wire Line
8000 4900 7200 4900
Wire Wire Line
3300 6500 2400 6500
Text HLabel 1900 6200 0 60 Input ~ 0
VCC_PIC
Text Label 2450 2400 0 60 ~ 0
VCC_PIC
Text Label 7200 4900 0 60 ~ 0
VCC_PIC
Text Label 9450 4700 0 60 ~ 0
VCC_PIC
Text Label 9450 2700 0 60 ~ 0
VCC_PIC
$Comp
L pic_programmer_schlib:GND #PWR036
U 1 1 442A8794
P 8000 5000
F 0 "#PWR036" H 8000 5000 30 0001 C CNN
F 1 "GND" H 8000 4930 30 0001 C CNN
F 2 "" H 8000 5000 60 0001 C CNN
F 3 "" H 8000 5000 60 0001 C CNN
1 8000 5000
0 1 1 0
$EndComp
Text Label 4750 4600 0 60 ~ 0
VCC_PIC
$Comp
L pic_programmer_schlib:GND #PWR037
U 1 1 443CCA5D
P 8000 4600
F 0 "#PWR037" H 8000 4600 30 0001 C CNN
F 1 "GND" H 8000 4530 30 0001 C CNN
F 2 "" H 8000 4600 60 0001 C CNN
F 3 "" H 8000 4600 60 0001 C CNN
1 8000 4600
0 1 1 0
$EndComp
NoConn ~ 8000 2900
NoConn ~ 9200 3200
NoConn ~ 9200 3100
NoConn ~ 9200 3000
NoConn ~ 9200 2900
NoConn ~ 9200 2600
NoConn ~ 9200 2500
NoConn ~ 9200 2400
NoConn ~ 9200 2300
NoConn ~ 9200 2200
NoConn ~ 9200 2100
NoConn ~ 8000 3200
NoConn ~ 8000 3100
NoConn ~ 8000 3000
NoConn ~ 8000 2800
NoConn ~ 8000 2700
NoConn ~ 8000 2500
NoConn ~ 8000 2400
NoConn ~ 8000 2300
NoConn ~ 8000 2200
NoConn ~ 8000 2100
NoConn ~ 8000 2000
$Comp
L pic_programmer_schlib:GND #PWR038
U 1 1 443697C7
P 9200 2800
F 0 "#PWR038" H 9200 2800 30 0001 C CNN
F 1 "GND" H 9200 2730 30 0001 C CNN
F 2 "" H 9200 2800 60 0001 C CNN
F 3 "" H 9200 2800 60 0001 C CNN
1 9200 2800
0 -1 -1 0
$EndComp
$Comp
L pic_programmer_schlib:GND #PWR039
U 1 1 443697C3
P 8000 2600
F 0 "#PWR039" H 8000 2600 30 0001 C CNN
F 1 "GND" H 8000 2530 30 0001 C CNN
F 2 "" H 8000 2600 60 0001 C CNN
F 3 "" H 8000 2600 60 0001 C CNN
1 8000 2600
0 1 1 0
$EndComp
Text Label 9350 2000 0 60 ~ 0
CLOCK-RB6
Text Label 9350 1900 0 60 ~ 0
DATA-RB7
Text Label 7350 1900 0 60 ~ 0
VPP-MCLR
$Comp
L pic_programmer_schlib:SUPP28 P2
U 1 1 4436967E
P 8600 2550
F 0 "P2" H 8600 3350 70 0000 C CNN
F 1 "SUPP28" H 8600 1700 70 0000 C CNN
F 2 "Package_DIP:DIP-28_W7.62mm_Socket_LongPads" H 8600 1600 15 0000 C CNN
F 3 "" H 8600 2550 60 0001 C CNN
1 8600 2550
1 0 0 -1
$EndComp
$Comp
L pic_programmer_schlib:GND #PWR040
U 1 1 442AA147
P 3300 6950
F 0 "#PWR040" H 3300 6950 30 0001 C CNN
F 1 "GND" H 3300 6880 30 0001 C CNN
F 2 "" H 3300 6950 60 0001 C CNN
F 3 "" H 3300 6950 60 0001 C CNN
1 3300 6950
1 0 0 -1
$EndComp
$Comp
L pic_programmer_schlib:C C7
U 1 1 442AA145
P 3300 6750
F 0 "C7" H 3350 6850 50 0000 L CNN
F 1 "100nF" H 3350 6650 50 0000 L CNN
F 2 "Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm" H 3500 6600 10 0000 C CNN
F 3 "" H 3300 6750 60 0001 C CNN
1 3300 6750
1 0 0 -1
$EndComp
$Comp
L pic_programmer_schlib:GND #PWR041
U 1 1 442AA138
P 2400 6950
F 0 "#PWR041" H 2400 6950 30 0001 C CNN
F 1 "GND" H 2400 6880 30 0001 C CNN
F 2 "" H 2400 6950 60 0001 C CNN
F 3 "" H 2400 6950 60 0001 C CNN
1 2400 6950
1 0 0 -1
$EndComp
NoConn ~ 9200 5800
NoConn ~ 9200 5700
NoConn ~ 9200 5600
NoConn ~ 9200 5500
NoConn ~ 9200 5400
NoConn ~ 9200 5300
NoConn ~ 9200 5200
NoConn ~ 9200 5100
NoConn ~ 9200 5000
NoConn ~ 9200 4900
NoConn ~ 9200 4600
NoConn ~ 9200 4500
NoConn ~ 9200 4400
NoConn ~ 9200 4300
NoConn ~ 9200 4200
NoConn ~ 9200 4100
NoConn ~ 8000 5800
NoConn ~ 8000 5700
NoConn ~ 8000 5600
NoConn ~ 8000 5500
NoConn ~ 8000 5400
NoConn ~ 8000 5300
NoConn ~ 8000 5200
NoConn ~ 8000 5100
NoConn ~ 8000 4800
NoConn ~ 8000 4700
NoConn ~ 8000 4500
NoConn ~ 8000 4400
NoConn ~ 8000 4300
NoConn ~ 8000 4200
NoConn ~ 8000 4100
NoConn ~ 8000 4000
$Comp
L pic_programmer_schlib:GND #PWR042
U 1 1 442A896A
P 9200 4800
F 0 "#PWR042" H 9200 4800 30 0001 C CNN
F 1 "GND" H 9200 4730 30 0001 C CNN
F 2 "" H 9200 4800 60 0001 C CNN
F 3 "" H 9200 4800 60 0001 C CNN
1 9200 4800
0 -1 -1 0
$EndComp
$Comp
L pic_programmer_schlib:SUPP40 P3
U 1 1 442A88ED
P 8600 4850
F 0 "P3" H 8600 5950 70 0000 C CNN
F 1 "SUPP40" H 8600 3700 70 0000 C CNN
F 2 "footprints:40tex-Ell600" H 8600 3600 15 0000 C CNN
F 3 "" H 8600 4850 60 0001 C CNN
1 8600 4850
1 0 0 -1
$EndComp
NoConn ~ 4400 1200
$Comp
L pic_programmer_schlib:GND #PWR043
U 1 1 442A8838
P 2800 1350
F 0 "#PWR043" H 2800 1350 30 0001 C CNN
F 1 "GND" H 2800 1280 30 0001 C CNN
F 2 "" H 2800 1350 60 0001 C CNN
F 3 "" H 2800 1350 60 0001 C CNN
1 2800 1350
1 0 0 -1
$EndComp
Text Label 4550 1500 0 60 ~ 0
DATA-RB7
Text Label 4550 1400 0 60 ~ 0
CLOCK-RB6
$Comp
L pic_programmer_schlib:24C16 U1
U 1 1 442A87F7
P 3700 1300
F 0 "U1" H 3850 1650 60 0000 C CNN
F 1 "24Cxx" H 3900 950 60 0000 C CNN
F 2 "Package_DIP:DIP-8_W7.62mm_Socket_LongPads" H 3900 900 10 0000 C CNN
F 3 "" H 3700 1300 60 0001 C CNN
1 3700 1300
1 0 0 -1
$EndComp
Text Label 9350 4000 0 60 ~ 0
CLOCK-RB6
Text Label 9350 3900 0 60 ~ 0
DATA-RB7
Text Label 7350 3900 0 60 ~ 0
VPP-MCLR
NoConn ~ 2950 4150
NoConn ~ 4500 5200
NoConn ~ 4500 5050
NoConn ~ 4500 4300
NoConn ~ 4500 4450
NoConn ~ 4500 4150
NoConn ~ 4500 4000
NoConn ~ 2950 5200
NoConn ~ 2950 5050
NoConn ~ 2950 4900
NoConn ~ 2950 4750
NoConn ~ 2950 4300
NoConn ~ 2950 4000
$Comp
L pic_programmer_schlib:PIC16F54 U5
U 1 1 442A81A7
P 3750 4600
F 0 "U5" H 3750 5350 60 0000 C CNN
F 1 "PIC_18_PINS" H 3750 3800 60 0000 C CNN
F 2 "Package_DIP:DIP-18_W7.62mm_Socket_LongPads" H 3800 3700 15 0000 C CNN
F 3 "" H 3750 4600 60 0001 C CNN
1 3750 4600
1 0 0 -1
$EndComp
NoConn ~ 4450 3400
NoConn ~ 3000 3100
NoConn ~ 3000 2700
Text Label 4650 4900 0 60 ~ 0
CLOCK-RB6
Text Label 4650 4750 0 60 ~ 0
DATA-RB7
Text Label 2300 4450 0 60 ~ 0
VPP-MCLR
Text Label 2350 3400 0 60 ~ 0
VPP-MCLR
Text Label 4600 3100 0 60 ~ 0
CLOCK-RB6
Text Label 4600 2700 0 60 ~ 0
DATA-RB7
Text HLabel 1900 6300 0 60 Input ~ 0
VPP-MCLR
Text HLabel 1900 2000 0 60 Input ~ 0
CLOCK-RB6
Text HLabel 1900 2100 0 60 Input ~ 0
DATA-RB7
$Comp
L pic_programmer_schlib:GND #PWR044
U 1 1 442A820F
P 2750 4650
F 0 "#PWR044" H 2750 4650 30 0001 C CNN
F 1 "GND" H 2750 4580 30 0001 C CNN
F 2 "" H 2750 4650 60 0001 C CNN
F 3 "" H 2750 4650 60 0001 C CNN
1 2750 4650
1 0 0 -1
$EndComp
$Comp
L pic_programmer_schlib:GND #PWR045
U 1 1 442A8205
P 4450 2400
F 0 "#PWR045" H 4450 2400 30 0001 C CNN
F 1 "GND" H 4450 2330 30 0001 C CNN
F 2 "" H 4450 2400 60 0001 C CNN
F 3 "" H 4450 2400 60 0001 C CNN
1 4450 2400
0 -1 -1 0
$EndComp
$Comp
L pic_programmer_schlib:PIC12C508A U6
U 1 1 442A81A5
P 3750 2900
F 0 "U6" H 3700 3600 60 0000 C CNN
F 1 "PIC_8_PINS" H 3750 2250 60 0000 C CNN
F 2 "Package_DIP:DIP-8_W7.62mm_Socket_LongPads" H 3750 2150 15 0000 C CNN
F 3 "" H 3750 2900 60 0001 C CNN
1 3750 2900
1 0 0 -1
$EndComp
$Comp
L pic_programmer_schlib:GND #PWR046
U 1 1 52C92629
P 3700 1850
F 0 "#PWR046" H 3700 1850 30 0001 C CNN
F 1 "GND" H 3700 1780 30 0001 C CNN
F 2 "" H 3700 1850 60 0001 C CNN
F 3 "" H 3700 1850 60 0001 C CNN
1 3700 1850
1 0 0 -1
$EndComp
Text Label 3700 800 0 60 ~ 0
VCC_PIC
$Comp
L pic_programmer_schlib:C C6
U 1 1 442AA12B
P 2400 6750
F 0 "C6" H 2450 6850 50 0000 L CNN
F 1 "100nF" H 2450 6650 50 0000 L CNN
F 2 "Capacitor_THT:C_Disc_D5.1mm_W3.2mm_P5.00mm" H 2600 6600 10 0000 C CNN
F 3 "" H 2400 6750 60 0001 C CNN
1 2400 6750
1 0 0 -1
$EndComp
Wire Wire Line
2400 6200 2400 6500
Text Label 2750 6500 0 60 ~ 0
VCC_PIC
Wire Wire Line
5300 1500 5300 2100
Connection ~ 5300 2700
Wire Wire Line
5400 1400 5400 2000
Connection ~ 5400 3100
Wire Wire Line
10000 1500 10000 1900
Connection ~ 5300 1500
Connection ~ 10000 1900
Wire Wire Line
10100 1400 10100 2000
Connection ~ 10100 2000
Connection ~ 5400 1400
Wire Wire Line
10200 6200 10200 4700
Wire Wire Line
5500 6200 5500 4600
Wire Wire Line
1900 6200 2100 6200
Connection ~ 10200 4700
Wire Wire Line
5500 800 3700 800
Connection ~ 5500 4600
Wire Wire Line
2200 3400 2200 4450
Wire Wire Line
7100 6300 2200 6300
Wire Wire Line
7100 1900 7100 3900
Connection ~ 2200 4450
Connection ~ 7100 3900
Wire Wire Line
7200 4900 7200 6200
Connection ~ 7200 6200
Connection ~ 5500 6200
Connection ~ 2200 6300
Wire Wire Line
2100 2400 2100 6200
Connection ~ 2100 6200
Wire Wire Line
1900 2000 5400 2000
Connection ~ 5400 2000
Wire Wire Line
1900 2100 5300 2100
Connection ~ 5300 2100
Connection ~ 2400 6500
Connection ~ 2400 6200
Wire Wire Line
3700 1850 3700 1800
Wire Wire Line
2400 6900 2400 6950
Wire Wire Line
3300 6900 3300 6950
$Comp
L pic_programmer_schlib:PWR_FLAG #FLG047
U 1 1 5558FA28
P 3300 6500
F 0 "#FLG047" H 3300 6595 30 0001 C CNN
F 1 "PWR_FLAG" H 3300 6680 30 0000 C CNN
F 2 "" H 3300 6500 60 0000 C CNN
F 3 "" H 3300 6500 60 0000 C CNN
1 3300 6500
0 1 1 0
$EndComp
Wire Wire Line
2800 1200 2800 1300
Wire Wire Line
2800 1300 2800 1350
Wire Wire Line
5300 2700 5300 4750
Wire Wire Line
5400 3100 5400 4900
Wire Wire Line
5300 1500 10000 1500
Wire Wire Line
10000 1900 10000 3900
Wire Wire Line
10100 2000 10100 4000
Wire Wire Line
5400 1400 10100 1400
Wire Wire Line
10200 4700 10200 2700
Wire Wire Line
5500 4600 5500 800
Wire Wire Line
2200 4450 2200 6300
Wire Wire Line
7100 3900 7100 6300
Wire Wire Line
7200 6200 10200 6200
Wire Wire Line
5500 6200 7200 6200
Wire Wire Line
2200 6300 1900 6300
Wire Wire Line
2100 6200 2400 6200
Wire Wire Line
5400 2000 5400 3100
Wire Wire Line
5300 2100 5300 2700
Wire Wire Line
2400 6500 2400 6600
Wire Wire Line
2400 6200 5500 6200
Connection ~ 3300 6500
$EndSCHEMATC

View File

@ -1,3 +1,3 @@
(sym_lib_table
(lib (name pic_programmer_schlib)(type Legacy)(uri ${KIPRJMOD}/libs/pic_programmer_schlib.lib)(options "")(descr ""))
(lib (name "pic_programmer_schlib")(type "KiCad")(uri "${KIPRJMOD}/libs/pic_programmer_schlib.kicad_sym")(options "")(descr ""))
)

View File

@ -1,199 +1,175 @@
(kicad_pcb (version 20171130) (host pcbnew "(2018-01-31 revision c758e72)-master")
(kicad_pcb (version 20201002) (generator pcbnew)
(general
(thickness 1.6002)
(drawings 0)
(tracks 4)
(zones 0)
(modules 4)
(nets 3)
)
(page A4)
(paper "A4")
(layers
(0 Dessus signal)
(31 Dessous signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
(0 "F.Cu" signal "Dessus")
(31 "B.Cu" signal "Dessous")
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(last_trace_width 0.2032)
(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2032)
(segment_width 0.381)
(edge_width 0.381)
(via_size 0.889)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3048)
(pcb_text_size 1.524 2.032)
(mod_edge_width 0.381)
(mod_text_size 1.524 1.524)
(mod_text_width 0.3048)
(pad_size 1.524 1.524)
(pad_drill 0.8128)
(pad_to_mask_clearance 0.254)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(layerselection 0x0000030_80000001)
(disableapertmacros false)
(usegerberextensions true)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(linewidth 0.150000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
(outputdirectory "")
)
)
(net 0 "")
(net 1 /NET1)
(net 2 /NET2)
(net 1 "/NET1")
(net 2 "/NET2")
(net_class Default "Ceci est la Netclass par défaut"
(clearance 0.254)
(trace_width 0.2032)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net /NET1)
(add_net /NET2)
)
(module 1pin (layer Dessus) (tedit 553E7303) (tstamp 4EE505BA)
(module "1pin" (layer "F.Cu") (tedit 5F95AABF) (tstamp 00000000-0000-0000-0000-00004ee505ba)
(at 89.535 45.593)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /4EDF7CC5)
(fp_text reference P1 (at 0 -12) (layer F.SilkS)
(tags "DEV")
(path "/00000000-0000-0000-0000-00004edf7cc5")
(attr through_hole)
(fp_text reference "P1" (at 0 -12) (layer "F.SilkS")
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 0cde0db0-d722-4364-93de-c9ef3b106ef4)
)
(fp_text value CONN_1 (at 0 12) (layer F.SilkS) hide
(fp_text value "CONN_1" (at 0 12) (layer "F.SilkS") hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 5e4f3802-ac60-4a91-88fb-961531b63561)
)
(fp_line (start -11 -11) (end 11 -11) (layer F.SilkS) (width 0.15))
(fp_line (start 11 -11) (end 11 11) (layer F.SilkS) (width 0.15))
(fp_line (start 11 11) (end -11 11) (layer F.SilkS) (width 0.15))
(fp_line (start -11 11) (end -11 -11) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at 0 0) (size 20.32 20.32) (layers Dessus F.Paste F.Mask)
(net 2 /NET2))
(pad 1 thru_hole circle (at -8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at -3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 0 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at 0 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at -3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(pad 1 thru_hole circle (at -8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(fp_line (start -11 -11) (end 11 -11) (layer "F.SilkS") (width 0.15) (tstamp 07532aef-c715-41d1-9c48-db5f03913fe8))
(fp_line (start -11 11) (end -11 -11) (layer "F.SilkS") (width 0.15) (tstamp 92a02999-a192-495f-bb12-4f5c45a5972f))
(fp_line (start 11 -11) (end 11 11) (layer "F.SilkS") (width 0.15) (tstamp 9ecc6a7f-6316-4fb1-9a6d-877714694934))
(fp_line (start 11 11) (end -11 11) (layer "F.SilkS") (width 0.15) (tstamp d3505e79-4ca0-4c1a-8116-65df111647be))
(pad "1" thru_hole circle (at 3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp 1d1c91af-2430-49bb-aa10-c85e31465067))
(pad "1" thru_hole circle (at -8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp 2d5ff131-583f-4b35-bf9c-4c69fb359fd5))
(pad "1" smd rect (at 0 0) (size 20.32 20.32) (layers "F.Cu" "F.Paste" "F.Mask")
(net 2 "/NET2") (tstamp 524ddc9b-4a8e-40f1-bab5-c794faaad669))
(pad "1" thru_hole circle (at -3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp 642daf42-cf9b-4f31-b756-055f16342b54))
(pad "1" thru_hole circle (at -3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp 78e511dc-d8f6-474a-8d1c-6a42560cb938))
(pad "1" thru_hole circle (at 3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp 7a2b20ed-df5e-4d40-ae20-5c178b193123))
(pad "1" thru_hole circle (at 8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp b1686322-1603-418b-834a-588ad11bf569))
(pad "1" thru_hole circle (at -8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp c162bfa2-ed71-444d-8ec1-15faab5a8aeb))
(pad "1" thru_hole circle (at 0 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp c41e3352-fe7e-4f1f-9a7f-dacef92b31c2))
(pad "1" thru_hole circle (at 0 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp c465f930-44c6-4eef-9fcb-d2319aeb3b0a))
(pad "1" thru_hole circle (at 8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp e15db349-8c4a-41d5-b95a-fb3865840e97))
)
(module 1pin (layer Dessus) (tedit 200000) (tstamp 4EE505BC)
(module "1pin" (layer "F.Cu") (tedit 5F95A9C2) (tstamp 00000000-0000-0000-0000-00004ee505bc)
(at 107.696 45.593)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /4EDF7CC0)
(fp_text reference P2 (at 0 -3.048) (layer F.SilkS)
(tags "DEV")
(path "/00000000-0000-0000-0000-00004edf7cc0")
(attr through_hole)
(fp_text reference "P2" (at 0.214 -3.163) (layer "F.SilkS")
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 63675ce0-5670-4022-a78a-e8dad835edb3)
)
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(fp_text value "CONN_1" (at 0.144 3.227) (layer "F.SilkS") hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 2abee844-1fc7-4133-a04f-0a70041ee2ff)
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS)
(net 2 /NET2))
(fp_circle (center 0 0) (end 0 -2.286) (layer "F.SilkS") (width 0.381) (tstamp 0e9c7ae8-ec29-4404-a610-c989c9302588))
(pad "1" thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 2 "/NET2") (tstamp feddcea1-e2f4-4733-980c-c44e9074b886))
)
(module 1pin (layer Dessus) (tedit 200000) (tstamp 4EE505BE)
(module "1pin" (layer "F.Cu") (tedit 5F95A9D4) (tstamp 00000000-0000-0000-0000-00004ee505be)
(at 87.122 61.468)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /4EE5056C)
(fp_text reference P3 (at 0 -3.048) (layer F.SilkS)
(tags "DEV")
(path "/00000000-0000-0000-0000-00004ee5056c")
(attr through_hole)
(fp_text reference "P3" (at -2.312 -2.858) (layer "F.SilkS")
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 148f3b4a-c700-45b6-a755-b0c42fc6902a)
)
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(fp_text value "CONN_1" (at -0.012 3.182) (layer "F.SilkS") hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp 5a9fac68-7c3b-4255-aac7-fbb0b08a7163)
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS)
(net 1 /NET1))
(fp_circle (center 0 0) (end 0 -2.286) (layer "F.SilkS") (width 0.381) (tstamp 13c78dfe-e522-4715-8ab5-867071caa69e))
(pad "1" thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 1 "/NET1") (tstamp 63e3e6f8-8b69-4903-a59f-e56ceec010ab))
)
(module 1pin (layer Dessus) (tedit 4EE8A1D1) (tstamp 4EE505C0)
(module "1pin" (layer "F.Cu") (tedit 5F95A9CC) (tstamp 00000000-0000-0000-0000-00004ee505c0)
(at 107.061 61.468)
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /4EE5056D)
(fp_text reference P4 (at 0 -3.048) (layer F.SilkS)
(tags "DEV")
(path "/00000000-0000-0000-0000-00004ee5056d")
(attr through_hole)
(fp_text reference "P4" (at 0 -3.048) (layer "F.SilkS")
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp f4fbe995-14c2-4175-8071-71e43d194df9)
)
(fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide
(fp_text value "CONN_1" (at 0 2.794) (layer "F.SilkS") hide
(effects (font (size 1.016 1.016) (thickness 0.254)))
(tstamp ce35a393-6d6e-47ea-adaf-ddd646280b2d)
)
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381))
(pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS)
(net 1 /NET1) (die_length 7.62))
(fp_circle (center 0 0) (end 0 -2.286) (layer "F.SilkS") (width 0.381) (tstamp 0f5d77d2-850f-4ebd-a4ba-437a96ef97e7))
(pad "1" thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask)
(net 1 "/NET1") (die_length 7.62) (tstamp e62dcc93-6e23-4dcc-a1d1-9cc59c15b145))
)
(segment (start 107.061 61.468) (end 87.122 61.468) (width 0.2032) (layer Dessous) (net 1))
(segment (start 103.759 41.148) (end 107.696 45.085) (width 0.2032) (layer Dessous) (net 2))
(segment (start 107.696 45.085) (end 107.696 45.593) (width 0.2032) (layer Dessous) (net 2))
(segment (start 97.79 41.148) (end 103.759 41.148) (width 0.2032) (layer Dessous) (net 2))
(gr_rect (start 68.05 23.5) (end 125.23 71.36) (layer "Edge.Cuts") (width 0.381) (tstamp a9cd5f86-b613-4436-a03d-d2c5e50ff2cf))
(segment (start 107.061 61.468) (end 87.122 61.468) (width 0.2032) (layer "B.Cu") (net 1) (tstamp 49c90b83-46f7-4695-9fb2-a36ccaefc53a))
(segment (start 107.696 45.085) (end 107.696 45.593) (width 0.2032) (layer "B.Cu") (net 2) (tstamp 02f6e7d9-28b2-458a-ac7b-f336cdd00b97))
(segment (start 103.759 41.148) (end 107.696 45.085) (width 0.2032) (layer "B.Cu") (net 2) (tstamp 877edd44-d1ee-4969-abbe-d908db78cdeb))
(segment (start 97.79 41.148) (end 103.759 41.148) (width 0.2032) (layer "B.Cu") (net 2) (tstamp c441df0a-fe2a-4190-af58-3556ba694ee1))
)

View File

@ -0,0 +1,378 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.381,
"copper_line_width": 0.381,
"copper_text_italic": false,
"copper_text_size_h": 1.524,
"copper_text_size_v": 2.032,
"copper_text_thickness": 0.30479999999999996,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.381,
"silk_text_italic": false,
"silk_text_size_h": 1.524,
"silk_text_size_v": 1.524,
"silk_text_thickness": 0.30479999999999996,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 1
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_too_small": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"keepout": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_too_small": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "error",
"silk_overlap": "error",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"via_hole_larger_than_pad": "error",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.01,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.127,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.508,
"min_track_width": 0.2032,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.889,
"solder_mask_clearance": 0.254,
"solder_mask_min_width": 0.0,
"solder_paste_clearance": 0.0,
"solder_paste_margin_ratio": 0.0
},
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_sheet_names": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "error",
"no_connect_dangling": "error",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"similar_labels": "warning",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "test_pads_inside_pads.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.254,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.127,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2032,
"via_diameter": 0.889,
"via_drill": 0.635,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"d83edf3e-df9e-48d3-b50a-87ddee1bc3a6",
""
]
],
"text_variables": {}
}

View File

@ -0,0 +1,145 @@
(kicad_sch (version 20201015) (generator eeschema)
(page 1 1)
(paper "A4")
(title_block
(date "19 dec 2011")
)
(lib_symbols
(symbol "test_pads_inside_pads_schlib:CONN_1" (pin_numbers hide) (pin_names (offset 0.762) hide) (in_bom yes) (on_board yes)
(property "Reference" "P" (id 0) (at 2.032 0 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 0 1.397 0)
(effects (font (size 0.762 0.762)))
)
(property "Footprint" "" (id 2) (at 0 0 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 0 0 0)
(effects (font (size 1.524 1.524)))
)
(symbol "CONN_1_0_1"
(circle (center 0 0) (radius 0.7874) (stroke (width 0)) (fill (type none)))
(polyline
(pts
(xy -0.762 0)
(xy -1.27 0)
)
(stroke (width 0)) (fill (type none))
)
)
(symbol "CONN_1_1_1"
(pin passive line (at -3.81 0 0) (length 2.54)
(name "1" (effects (font (size 1.524 1.524))))
(number "1" (effects (font (size 1.524 1.524))))
)
)
)
)
(wire (pts (xy 105.41 36.83) (xy 95.25 36.83))
(stroke (width 0) (type solid) (color 0 0 0 0))
)
(wire (pts (xy 105.41 44.45) (xy 95.25 44.45))
(stroke (width 0) (type solid) (color 0 0 0 0))
)
(label "NET1" (at 97.79 36.83 0)
(effects (font (size 1.524 1.524)) (justify left bottom))
)
(label "NET2" (at 97.79 44.45 0)
(effects (font (size 1.524 1.524)) (justify left bottom))
)
(symbol (lib_id "test_pads_inside_pads_schlib:CONN_1") (at 91.44 36.83 180) (unit 1)
(in_bom yes) (on_board yes)
(uuid "00000000-0000-0000-0000-00004ee5056c")
(property "Reference" "P3" (id 0) (at 89.408 36.83 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 91.44 38.227 0)
(effects (font (size 0.762 0.762)) hide)
)
(property "Footprint" "Connect:1pin" (id 2) (at 91.44 38.1 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 91.44 36.83 0)
(effects (font (size 1.524 1.524)) hide)
)
)
(symbol (lib_id "test_pads_inside_pads_schlib:CONN_1") (at 91.44 44.45 180) (unit 1)
(in_bom yes) (on_board yes)
(uuid "00000000-0000-0000-0000-00004edf7cc5")
(property "Reference" "P1" (id 0) (at 89.408 44.45 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 91.44 45.847 0)
(effects (font (size 0.762 0.762)) hide)
)
(property "Footprint" "Connect:1pin" (id 2) (at 91.44 45.72 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 91.44 44.45 0)
(effects (font (size 1.524 1.524)) hide)
)
)
(symbol (lib_id "test_pads_inside_pads_schlib:CONN_1") (at 109.22 36.83 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid "00000000-0000-0000-0000-00004ee5056d")
(property "Reference" "P4" (id 0) (at 111.252 36.83 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 109.22 35.433 0)
(effects (font (size 0.762 0.762)) hide)
)
(property "Footprint" "Connect:1pin" (id 2) (at 109.22 38.1 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 109.22 36.83 0)
(effects (font (size 1.524 1.524)) hide)
)
)
(symbol (lib_id "test_pads_inside_pads_schlib:CONN_1") (at 109.22 44.45 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid "00000000-0000-0000-0000-00004edf7cc0")
(property "Reference" "P2" (id 0) (at 111.252 44.45 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 109.22 43.053 0)
(effects (font (size 0.762 0.762)) hide)
)
(property "Footprint" "Connect:1pin" (id 2) (at 109.22 45.72 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 109.22 44.45 0)
(effects (font (size 1.524 1.524)) hide)
)
)
(sheet_instances
(path "/" (page "1"))
)
(symbol_instances
(path "/00000000-0000-0000-0000-00004edf7cc5"
(reference "P1") (unit 1) (value "CONN_1") (footprint "Connect:1pin")
)
(path "/00000000-0000-0000-0000-00004edf7cc0"
(reference "P2") (unit 1) (value "CONN_1") (footprint "Connect:1pin")
)
(path "/00000000-0000-0000-0000-00004ee5056c"
(reference "P3") (unit 1) (value "CONN_1") (footprint "Connect:1pin")
)
(path "/00000000-0000-0000-0000-00004ee5056d"
(reference "P4") (unit 1) (value "CONN_1") (footprint "Connect:1pin")
)
)
)

View File

@ -1,58 +0,0 @@
(export (version D)
(design
(source F:\kicad-launchpad\git_testing\demos\test_pads_inside_pads\test_pads_inside_pads.sch)
(date "21/11/2017 21:03:00")
(tool "Eeschema (2017-11-21 revision 945325d)-master")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title)
(company)
(rev)
(date "19 dec 2011")
(source test_pads_inside_pads.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value ""))
(comment (number 4) (value "")))))
(components
(comp (ref P4)
(value CONN_1)
(footprint Connect:1pin)
(libsource (lib test_pads_inside_pads_schlib) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 4EE5056D))
(comp (ref P3)
(value CONN_1)
(footprint Connect:1pin)
(libsource (lib test_pads_inside_pads_schlib) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 4EE5056C))
(comp (ref P1)
(value CONN_1)
(footprint Connect:1pin)
(libsource (lib test_pads_inside_pads_schlib) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 4EDF7CC5))
(comp (ref P2)
(value CONN_1)
(footprint Connect:1pin)
(libsource (lib test_pads_inside_pads_schlib) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 4EDF7CC0)))
(libparts
(libpart (lib test_pads_inside_pads_schlib) (part CONN_1)
(fields
(field (name Reference) P)
(field (name Value) CONN_1))
(pins
(pin (num 1) (name 1) (type passive)))))
(libraries
(library (logical test_pads_inside_pads_schlib)
(uri F:\kicad-launchpad\git_testing\demos\test_pads_inside_pads/test_pads_inside_pads_schlib.lib)))
(nets
(net (code 1) (name /NET1)
(node (ref P4) (pin 1))
(node (ref P3) (pin 1)))
(net (code 2) (name /NET2)
(node (ref P1) (pin 1))
(node (ref P2) (pin 1)))))

View File

@ -0,0 +1,32 @@
(kicad_symbol_lib (version 20201005) (generator kicad_symbol_editor)
(symbol "test_pads_inside_pads_schlib:CONN_1" (pin_numbers hide) (pin_names (offset 0.762) hide) (in_bom yes) (on_board yes)
(property "Reference" "P" (id 0) (at 2.032 0 0)
(effects (font (size 1.016 1.016)) (justify left))
)
(property "Value" "CONN_1" (id 1) (at 0 1.397 0)
(effects (font (size 0.762 0.762)))
)
(property "Footprint" "" (id 2) (at 0 0 0)
(effects (font (size 1.524 1.524)))
)
(property "Datasheet" "" (id 3) (at 0 0 0)
(effects (font (size 1.524 1.524)))
)
(symbol "CONN_1_0_1"
(circle (center 0 0) (radius 0.7874) (stroke (width 0)) (fill (type none)))
(polyline
(pts
(xy -0.762 0)
(xy -1.27 0)
)
(stroke (width 0)) (fill (type none))
)
)
(symbol "CONN_1_1_1"
(pin passive line (at -3.81 0 0) (length 2.54)
(name "1" (effects (font (size 1.524 1.524))))
(number "1" (effects (font (size 1.524 1.524))))
)
)
)
)