Allow vias to connect <no net> tracks even when DRC checking is on.
Fixes https://gitlab.com/kicad/code/kicad/issues/12403
(cherry picked from commit eaccd40c75
)
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@ -2413,24 +2413,25 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
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return false;
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return false;
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DRC_CONSTRAINT constraint;
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DRC_CONSTRAINT constraint;
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int clearance;
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BOARD_CONNECTED_ITEM* connectedItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aOther );
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ZONE* zone = dynamic_cast<ZONE*>( aOther );
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if( ( aOther->Type() == PCB_ZONE_T || aOther->Type() == PCB_FP_ZONE_T )
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if( zone && zone->GetIsRuleArea() )
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&& static_cast<ZONE*>( aOther )->GetIsRuleArea() )
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{
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{
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ZONE* ruleArea = static_cast<ZONE*>( aOther );
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if( zone->GetDoNotAllowVias() )
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return zone->Outline()->Collide( aVia->GetPosition(), aVia->GetWidth() / 2 );
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if( ruleArea->GetDoNotAllowVias() )
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return ruleArea->Outline()->Collide( aVia->GetPosition(), aVia->GetWidth() / 2 );
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return false;
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return false;
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}
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}
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BOARD_CONNECTED_ITEM* cItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( aOther );
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if( connectedItem )
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{
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int connectedItemNet = connectedItem->GetNetCode();
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if( cItem && cItem->GetNetCode() == aVia->GetNetCode() )
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if( connectedItemNet == 0 || connectedItemNet == aVia->GetNetCode() )
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return false;
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return false;
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}
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int clearance;
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for( PCB_LAYER_ID layer : aOther->GetLayerSet().Seq() )
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for( PCB_LAYER_ID layer : aOther->GetLayerSet().Seq() )
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{
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{
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