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Fix a few I18N issues.

This commit is contained in:
jean-pierre charras 2020-09-14 10:02:07 +02:00
parent 748bee1bc7
commit ff0a728753
3 changed files with 31 additions and 30 deletions
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18
pcbnew/drc/drc_engine.cpp
View File

@ -104,7 +104,7 @@ void DRC_ENGINE::loadImplicitRules()
DRC_CONSTRAINT annulusConstraint( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH );
annulusConstraint.Value().SetMin( bds.m_ViasMinAnnulus );
rule->AddConstraint( annulusConstraint );
DRC_CONSTRAINT diameterConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
rule->AddConstraint( diameterConstraint );
@ -159,7 +159,7 @@ void DRC_ENGINE::loadImplicitRules()
m_board->SynchronizeNetsAndNetClasses();
netclasses.push_back( bds.GetNetClasses().GetDefault() );
for( const std::pair<const wxString, NETCLASSPTR>& netclass : bds.GetNetClasses() )
netclasses.push_back( netclass.second );
@ -173,7 +173,7 @@ void DRC_ENGINE::loadImplicitRules()
className );
DRC_RULE_CONDITION* inNetclassCondition = new DRC_RULE_CONDITION ( expr );
DRC_RULE* netclassRule = createImplicitRule( wxString::Format( _( "netclass '%s'" ),
className ));
@ -488,10 +488,10 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_TYPE_T aConstraintI
const CONSTRAINT_WITH_CONDITIONS* rcons = ruleset->sortedConstraints[ ii ];
bool implicit = rcons->parentRule && rcons->parentRule->m_Implicit;
REPORT( wxString::Format( _( "Checking %s %s." ),
implicit ? _( "" ) : _( "rule" ),
rcons->parentRule->m_Name ) )
if( implicit )
REPORT( wxString::Format( _( "Checking %s." ), rcons->parentRule->m_Name ) )
else
REPORT( wxString::Format( _( "Checking rule %s." ), rcons->parentRule->m_Name ) )
if( aLayer != UNDEFINED_LAYER && !rcons->layerTest.test( aLayer ) )
{
REPORT( wxString::Format( _( "Rule layer \"%s\" not matched." ),
@ -556,9 +556,9 @@ void DRC_ENGINE::ReportViolation( const std::shared_ptr<DRC_ITEM>& aItem, wxPoin
if( rule )
msg += wxString::Format( ", violating rule: '%s'", rule->m_Name );
m_reporter->Report( msg );
wxString violatingItemsStr = "Violating items: ";
m_reporter->Report( wxString::Format( " |- violating position (%d, %d)",

2
pcbnew/pcb_expr_evaluator.cpp
View File

@ -72,7 +72,7 @@ static void onLayer( LIBEVAL::CONTEXT* aCtx, void *self )
}
if( !anyMatch )
aCtx->ReportError( wxString::Format( _( "Unrecognized layer '%s' " ), layerName ) );
aCtx->ReportError( wxString::Format( _( "Unrecognized layer '%s'" ), layerName ) );
}

41
pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp
View File

@ -50,19 +50,20 @@ void CADSTAR_PCB_ARCHIVE_LOADER::Load( ::BOARD* aBoard )
//Note: can't use getKiCadPoint() due wxPoint being int - need long long to make the check
long long designSizeXkicad = (long long) designLimit.x * KiCadUnitMultiplier;
long long designSizeYkicad = (long long) designLimit.y * KiCadUnitMultiplier;
// Max size limited by the positive dimention of wxPoint
long long maxDesignSizekicad = (long long) std::numeric_limits<int>::max();
double maxDesignSizekicad = Iu2Millimeter( std::numeric_limits<int>::max() );
if( designSizeXkicad > maxDesignSizekicad || designSizeYkicad > maxDesignSizekicad )
THROW_IO_ERROR( wxString::Format(
_( "The design is too large and cannot be imported into KiCad. \n"
"Please reduce the maximum design size in CADSTAR by navigating to: \n"
"Design Tab -> Properties -> Design Options -> Maximum Design Size. \n"
"Current Design size: %.2f, %.2f milimetres. \n"
"Maximum permitted design size: %.2f, %.2f milimetres.\n" ),
(double) designSizeXkicad / 1E6, (double) designSizeYkicad / 1E6,
(double) maxDesignSizekicad / 1E6, (double) maxDesignSizekicad / 1E6 ) );
"Current Design size: %.2f, %.2f millimeters. \n"
"Maximum permitted design size: %.2f, %.2f millimeters.\n" ),
(double) designSizeXkicad / PCB_IU_PER_MM,
(double) designSizeYkicad / PCB_IU_PER_MM,
maxDesignSizekicad, maxDesignSizekicad ) );
mDesignCenter =
( Assignments.Technology.DesignArea.first + Assignments.Technology.DesignArea.second )
@ -416,19 +417,19 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadDesignRules()
applyRule( "T_T", &ds.m_MinClearance );
applyRule( "C_B", &ds.m_CopperEdgeClearance );
applyRule( "H_H", &ds.m_HoleToHoleMin );
applyRule( "H_H", &ds.m_HoleToHoleMin );
ds.m_TrackMinWidth = Assignments.Technology.MinRouteWidth;
auto applyNetClassRule =
[&]( wxString aID, ::NETCLASS* aNetClassPtr, void (::NETCLASS::*aFunc)(int) )
[&]( wxString aID, ::NETCLASS* aNetClassPtr, void (::NETCLASS::*aFunc)(int) )
{
int value = -1;
applyRule(aID, &value);
if( value != -1 )
(aNetClassPtr->*aFunc)(value);
};
applyNetClassRule( "T_T", ds.GetDefault(), &::NETCLASS::SetClearance );
@ -585,7 +586,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadLibraryPads( const SYMDEF& aComponent, MODU
if( csPadcode.Shape.Size == 0 )
// zero sized pads seems to break KiCad so lets make it very small instead
csPadcode.Shape.Size = 1;
csPadcode.Shape.Size = 1;
switch( csPadcode.Shape.ShapeType )
{
@ -1104,7 +1105,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadTemplates()
wxASSERT( Assignments.Layerdefs.Layers.find( layer ) != Assignments.Layerdefs.Layers.end() );
//The net name will equal the layer name
wxString powerPlaneLayerName = Assignments.Layerdefs.Layers.at( layer ).Name;
wxString powerPlaneLayerName = Assignments.Layerdefs.Layers.at( layer ).Name;
NET_ID netid = wxEmptyString;
for( std::pair<NET_ID, NET> netPair : Layout.Nets )
@ -1149,9 +1150,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadTemplates()
}
}
}
@ -1247,7 +1248,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNets()
{
NET net = netPair.second;
wxString netnameForErrorReporting = net.Name;
if( netnameForErrorReporting.IsEmpty() )
netnameForErrorReporting = "$" + net.SignalNum;
@ -1269,7 +1270,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNets()
{
NET::PIN pin = pinPair.second;
MODULE* m = getModuleFromCadstarID( pin.ComponentID );
if( m == nullptr )
{
wxLogWarning( wxString::Format(
@ -1346,7 +1347,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks(
dsVector.push_back( ds );
prevEnd = v.Vertex.End;
}
//Todo add real netcode to the tracks
std::vector<TRACK*> tracks =
makeTracksFromDrawsegments( dsVector, mBoard, getKiCadNet( aCadstarNetID ) );
@ -1540,7 +1541,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::drawCadstarText( const TEXT& aCadstarText,
else
{
txt->SetLayer( getKiCadLayer( layersToDrawOn ) );
if( !aCadstarGroupID.IsEmpty() )
addToGroup( aCadstarGroupID, txt );
}
@ -1829,7 +1830,7 @@ SHAPE_POLY_SET CADSTAR_PCB_ARCHIVE_LOADER::getPolySetFromCadstarShape( const SHA
for( int i = 0; i < polySet.OutlineCount(); ++i )
{
wxASSERT( polySet.Outline( i ).PointCount() > 2 );
for( int j = 0; j < polySet.HoleCount( i ); ++j )
{
wxASSERT( polySet.Hole( i, j ).PointCount() > 2 );
@ -2337,7 +2338,7 @@ NETINFO_ITEM* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadNet( const NET_ID& aCadstarNet
else
{
wxCHECK( Layout.Nets.find( aCadstarNetID ) != Layout.Nets.end(), nullptr );
NET csNet = Layout.Nets.at( aCadstarNetID );
wxString newName = csNet.Name;
@ -2349,7 +2350,7 @@ NETINFO_ITEM* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadNet( const NET_ID& aCadstarNet
NET::PIN firstPin = (*csNet.Pins.begin()).second;
//we should have already loaded the component with loadComponents() :
MODULE* m = getModuleFromCadstarID( firstPin.ComponentID );
MODULE* m = getModuleFromCadstarID( firstPin.ComponentID );
newName = wxT( "Net-(" );
newName << m->Reference().GetText();
newName << "-Pad" << wxString::Format( "%i", firstPin.PadID) << ")";