CADSTAR PCB Archive Importer: Rewrite loadBoardStackup routine
Uses BOARD_STACKUP::BuildDefaultStackupList instead of trying to build the stackup from scratch Fixes several asserts / incorrect stackups in some older boards
This commit is contained in:
Roberto Fernandez Bautista
Wayne Stambaugh
parent
a2cbbb963e
commit
ffee24be63
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@ -129,129 +129,6 @@ void CADSTAR_PCB_ARCHIVE_LOADER::Load( ::BOARD* aBoard, ::PROJECT* aProject )
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}
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BOARD_STACKUP_ITEM_TYPE CADSTAR_PCB_ARCHIVE_LOADER::getStackupItemType(
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const PCB_LAYER_ID& aKiCadLayer )
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{
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// Stackup item type can be (mostly) inferred from the PCB_LAYER_ID
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switch( aKiCadLayer )
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{
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case PCB_LAYER_ID::F_Cu:
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case PCB_LAYER_ID::In1_Cu:
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case PCB_LAYER_ID::In2_Cu:
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case PCB_LAYER_ID::In3_Cu:
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case PCB_LAYER_ID::In4_Cu:
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case PCB_LAYER_ID::In5_Cu:
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case PCB_LAYER_ID::In6_Cu:
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case PCB_LAYER_ID::In7_Cu:
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case PCB_LAYER_ID::In8_Cu:
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case PCB_LAYER_ID::In9_Cu:
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case PCB_LAYER_ID::In10_Cu:
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case PCB_LAYER_ID::In11_Cu:
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case PCB_LAYER_ID::In12_Cu:
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case PCB_LAYER_ID::In13_Cu:
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case PCB_LAYER_ID::In14_Cu:
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case PCB_LAYER_ID::In15_Cu:
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case PCB_LAYER_ID::In16_Cu:
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case PCB_LAYER_ID::In17_Cu:
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case PCB_LAYER_ID::In18_Cu:
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case PCB_LAYER_ID::In19_Cu:
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case PCB_LAYER_ID::In20_Cu:
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case PCB_LAYER_ID::In21_Cu:
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case PCB_LAYER_ID::In22_Cu:
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case PCB_LAYER_ID::In23_Cu:
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case PCB_LAYER_ID::In24_Cu:
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case PCB_LAYER_ID::In25_Cu:
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case PCB_LAYER_ID::In26_Cu:
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case PCB_LAYER_ID::In27_Cu:
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case PCB_LAYER_ID::In28_Cu:
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case PCB_LAYER_ID::In29_Cu:
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case PCB_LAYER_ID::In30_Cu:
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case PCB_LAYER_ID::B_Cu:
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_COPPER;
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case PCB_LAYER_ID::B_Paste:
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case PCB_LAYER_ID::F_Paste:
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_SOLDERPASTE;
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case PCB_LAYER_ID::B_SilkS:
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case PCB_LAYER_ID::F_SilkS:
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_SILKSCREEN;
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case PCB_LAYER_ID::B_Mask:
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case PCB_LAYER_ID::F_Mask:
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_SOLDERMASK;
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case PCB_LAYER_ID::UNDEFINED_LAYER:
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//Special case: if undefined layer we assume that it was a dielectric layer
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_DIELECTRIC;
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default:
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break;
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}
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// All other layers are documentation/not part of the stackup
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return BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_UNDEFINED;
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}
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wxString CADSTAR_PCB_ARCHIVE_LOADER::getLayerTypeName( const PCB_LAYER_ID& aKiCadLayer )
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{
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// Layer type name can be inferred from the KiCad layer unless it is a dielectric layer
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switch( aKiCadLayer )
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{
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case PCB_LAYER_ID::F_Cu:
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case PCB_LAYER_ID::In1_Cu:
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case PCB_LAYER_ID::In2_Cu:
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case PCB_LAYER_ID::In3_Cu:
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case PCB_LAYER_ID::In4_Cu:
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case PCB_LAYER_ID::In5_Cu:
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case PCB_LAYER_ID::In6_Cu:
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case PCB_LAYER_ID::In7_Cu:
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case PCB_LAYER_ID::In8_Cu:
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case PCB_LAYER_ID::In9_Cu:
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case PCB_LAYER_ID::In10_Cu:
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case PCB_LAYER_ID::In11_Cu:
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case PCB_LAYER_ID::In12_Cu:
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case PCB_LAYER_ID::In13_Cu:
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case PCB_LAYER_ID::In14_Cu:
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case PCB_LAYER_ID::In15_Cu:
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case PCB_LAYER_ID::In16_Cu:
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case PCB_LAYER_ID::In17_Cu:
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case PCB_LAYER_ID::In18_Cu:
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case PCB_LAYER_ID::In19_Cu:
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case PCB_LAYER_ID::In20_Cu:
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case PCB_LAYER_ID::In21_Cu:
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case PCB_LAYER_ID::In22_Cu:
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case PCB_LAYER_ID::In23_Cu:
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case PCB_LAYER_ID::In24_Cu:
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case PCB_LAYER_ID::In25_Cu:
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case PCB_LAYER_ID::In26_Cu:
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case PCB_LAYER_ID::In27_Cu:
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case PCB_LAYER_ID::In28_Cu:
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case PCB_LAYER_ID::In29_Cu:
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case PCB_LAYER_ID::In30_Cu:
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case PCB_LAYER_ID::B_Cu: return KEY_COPPER;
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case PCB_LAYER_ID::B_Paste: return _HKI( "Bottom Solder Paste" );
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case PCB_LAYER_ID::F_Paste: return _HKI( "Top Solder Paste" );
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case PCB_LAYER_ID::B_SilkS: return _HKI( "Bottom Silk Screen" );
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case PCB_LAYER_ID::F_SilkS: return _HKI( "Top Silk Screen" );
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case PCB_LAYER_ID::B_Mask: return _HKI( "Bottom Solder Mask" );
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case PCB_LAYER_ID::F_Mask: return _HKI( "Top Solder Mask" );
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//Special case: if undefined layer we assume that it was a dielectric layer (prepreg)
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case PCB_LAYER_ID::UNDEFINED_LAYER: return KEY_PREPREG;
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default: break;
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}
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// All other layers do not have a type name
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return wxEmptyString;
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}
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void CADSTAR_PCB_ARCHIVE_LOADER::logBoardStackupWarning(
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const wxString& aCadstarLayerName,
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const PCB_LAYER_ID& aKiCadLayer )
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@ -279,44 +156,248 @@ void CADSTAR_PCB_ARCHIVE_LOADER::logBoardStackupMessage( const wxString& aCadsta
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}
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void CADSTAR_PCB_ARCHIVE_LOADER::initStackupItem( const LAYER& aCadstarLayer,
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::BOARD_STACKUP_ITEM* aKiCadItem,
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int aDielectricSublayer )
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{
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if( !aCadstarLayer.MaterialId.IsEmpty() )
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{
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MATERIAL material = Assignments.Layerdefs.Materials.at( aCadstarLayer.MaterialId );
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aKiCadItem->SetMaterial( material.Name, aDielectricSublayer );
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aKiCadItem->SetEpsilonR( material.Permittivity.GetDouble(), aDielectricSublayer );
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aKiCadItem->SetLossTangent( material.LossTangent.GetDouble(), aDielectricSublayer );
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//TODO add Resistivity when KiCad supports it
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}
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aKiCadItem->SetLayerName( aCadstarLayer.Name );
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aKiCadItem->SetThickness( getKiCadLength( aCadstarLayer.Thickness ), aDielectricSublayer );
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}
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void CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup()
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{
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std::map<LAYER_ID, LAYER>& cpaLayers = Assignments.Layerdefs.Layers;
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std::map<MATERIAL_ID, MATERIAL>& cpaMaterials = Assignments.Layerdefs.Materials;
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std::vector<LAYER_ID>& cpaLayerStack = Assignments.Layerdefs.LayerStack;
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unsigned numElecAndPowerLayers = 0;
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BOARD_DESIGN_SETTINGS& designSettings = mBoard->GetDesignSettings();
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BOARD_STACKUP& stackup = designSettings.GetStackupDescriptor();
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int noOfKiCadStackupLayers = 0;
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int lastElectricalLayerIndex = 0;
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int dielectricSublayer = 0;
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int numDielectricLayers = 0;
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bool prevWasDielectric = false;
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BOARD_STACKUP_ITEM* tempKiCadLayer = nullptr;
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std::vector<PCB_LAYER_ID> layerIDs;
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//Remove all layers except required ones
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stackup.RemoveAll();
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layerIDs.push_back( PCB_LAYER_ID::F_CrtYd );
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layerIDs.push_back( PCB_LAYER_ID::B_CrtYd );
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layerIDs.push_back( PCB_LAYER_ID::Margin );
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layerIDs.push_back( PCB_LAYER_ID::Edge_Cuts );
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designSettings.SetEnabledLayers( LSET( &layerIDs[0], layerIDs.size() ) );
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for( auto it = cpaLayerStack.begin(); it != cpaLayerStack.end(); ++it )
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// Structure describing an electrical layer with optional dielectric layers below it
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// (construction layers in CADSTAR)
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struct LAYER_BLOCK
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{
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LAYER_T copperType = LAYER_T::LT_UNDEFINED;
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PCB_LAYER_ID kicadLayerID = PCB_LAYER_ID::UNDEFINED_LAYER;
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wxString layerTypeName = wxEmptyString;
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LAYER_ID ElecLayerID = wxEmptyString; // Normally not empty, but could be empty if the
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// first layer in the stackup is a construction
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// layer
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std::vector<LAYER_ID> ConstructionLayers; // Normally empty for the last electrical layer
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// but it is possible to build a board in CADSTAR
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// with no construction layers or with the bottom
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// layer being a construction layer
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if( cpaLayers.find( *it ) == cpaLayers.end() )
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bool IsInitialised() { return !ElecLayerID.IsEmpty() || ConstructionLayers.size() > 0; };
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};
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std::vector<LAYER_BLOCK> cadstarBoardStackup;
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LAYER_BLOCK currentBlock;
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// Find the electrical and construction (dielectric) layers in the stackup
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for( LAYER_ID cadstarLayerID : Assignments.Layerdefs.LayerStack )
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{
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LAYER cadstarLayer = Assignments.Layerdefs.Layers.at( cadstarLayerID );
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if( cadstarLayer.Type == LAYER_TYPE::JUMPERLAYER ||
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cadstarLayer.Type == LAYER_TYPE::POWER ||
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cadstarLayer.Type == LAYER_TYPE::ELEC )
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{
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THROW_IO_ERROR( _( "The selected file is not valid or might be corrupt: The layer "
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"stack refers to layer ID '%s' which does not exist in the layer "
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"definitions." ) );
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if( currentBlock.IsInitialised() )
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{
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cadstarBoardStackup.push_back( currentBlock );
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currentBlock = LAYER_BLOCK(); // reset the block
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}
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currentBlock.ElecLayerID = cadstarLayerID;
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}
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else if( cadstarLayer.Type == LAYER_TYPE::CONSTRUCTION )
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{
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currentBlock.ConstructionLayers.push_back( cadstarLayerID );
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}
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}
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if( currentBlock.IsInitialised() )
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cadstarBoardStackup.push_back( currentBlock );
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int totalCopperLayers = cadstarBoardStackup.size();
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// Special case: last layer in the stackup is a construction layer, we need to use B.Cu as a
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// dummy layer
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if( cadstarBoardStackup.back().ConstructionLayers.size() > 0 )
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{
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cadstarBoardStackup.push_back( LAYER_BLOCK() ); //Add dummy layer at the end
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++totalCopperLayers;
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}
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// Make sure it is an even number of layers (KiCad doesn't yet support unbalanced stack-ups)
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if( ( totalCopperLayers % 2 ) != 0 )
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{
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LAYER_BLOCK bottomLayer = cadstarBoardStackup.back();
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cadstarBoardStackup.pop_back();
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LAYER_BLOCK secondToLastLayer = cadstarBoardStackup.back();
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cadstarBoardStackup.pop_back();
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LAYER_BLOCK dummyLayer;
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LAYER_ID lastConstruction = secondToLastLayer.ConstructionLayers.back();
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if( secondToLastLayer.ConstructionLayers.size() > 1 )
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{
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// At least two construction layers, lets remove it here and use it in the dummy layer
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secondToLastLayer.ConstructionLayers.pop_back();
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}
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else
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{
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// There is only one construction layer, lets halve its thickness so it is split evenly
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// between this layer and the dummy layer
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Assignments.Layerdefs.Layers.at( lastConstruction ).Thickness /= 2;
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}
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LAYER curLayer = cpaLayers.at( *it );
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dummyLayer.ConstructionLayers.push_back( lastConstruction );
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cadstarBoardStackup.push_back( secondToLastLayer );
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cadstarBoardStackup.push_back( dummyLayer );
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cadstarBoardStackup.push_back( bottomLayer );
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++totalCopperLayers;
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}
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wxASSERT( totalCopperLayers == cadstarBoardStackup.size() );
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wxASSERT( cadstarBoardStackup.back().ConstructionLayers.size() == 0 );
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// Create a new stackup from default stackup list
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BOARD_STACKUP& stackup = mBoard->GetDesignSettings().GetStackupDescriptor();
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stackup.RemoveAll();
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mBoard->SetEnabledLayers( LSET::AllLayersMask() );
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mBoard->SetVisibleLayers( LSET::AllLayersMask() );
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mBoard->SetCopperLayerCount( totalCopperLayers );
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stackup.BuildDefaultStackupList( &mBoard->GetDesignSettings(), totalCopperLayers );
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size_t stackIndex = 0;
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for( BOARD_STACKUP_ITEM* item : stackup.GetList() )
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{
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if( item->GetType() == BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_COPPER )
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{
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LAYER_ID layerID = cadstarBoardStackup.at( stackIndex ).ElecLayerID;
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if( layerID.IsEmpty() )
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{
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// Loading a dummy layer. Make zero thickness so it doesn't affect overall stackup
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item->SetThickness( 0 );
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}
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else
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{
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LAYER copperLayer = Assignments.Layerdefs.Layers.at( layerID );
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initStackupItem( copperLayer, item, 0 );
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LAYER_T copperType = LAYER_T::LT_SIGNAL;
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switch( copperLayer.Type )
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{
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case LAYER_TYPE::JUMPERLAYER:
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copperType = LAYER_T::LT_JUMPER;
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break;
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case LAYER_TYPE::ELEC:
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copperType = LAYER_T::LT_SIGNAL;
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break;
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case LAYER_TYPE::POWER:
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copperType = LAYER_T::LT_POWER;
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mPowerPlaneLayers.push_back( copperLayer.ID ); //need to add a Copper zone
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break;
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default:
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wxFAIL_MSG( "Unexpected Layer type. Was expecting an electrical type" );
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break;
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}
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mBoard->SetLayerType( item->GetBrdLayerId(), copperType );
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mBoard->SetLayerName( item->GetBrdLayerId(), item->GetLayerName() );
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mCopperLayers.insert( { copperLayer.PhysicalLayer, copperLayer.ID } );
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mLayermap.insert( { copperLayer.ID, item->GetBrdLayerId() } );
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}
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}
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else if( item->GetType() == BOARD_STACKUP_ITEM_TYPE::BS_ITEM_TYPE_DIELECTRIC )
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{
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LAYER_BLOCK layerBlock = cadstarBoardStackup.at( stackIndex );
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LAYER_BLOCK layerBlockBelow = cadstarBoardStackup.at( stackIndex + 1 );
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// We should have made sure all layer blocks have at least one construction layer
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wxASSERT( layerBlock.ConstructionLayers.size() > 0 );
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int dielectricId = stackIndex + 1;
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// item->SetBrdLayerId();
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item->SetDielectricLayerId( dielectricId );
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//Prepreg or core?
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//Look at CADSTAR layer embedding (see LAYER->Embedding) to check whether the electrical
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//layer embeds above and below to decide if current layer is prepreg or core
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if( layerBlock.ElecLayerID.IsEmpty() )
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{
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//Dummy electrical layer, assume prepreg
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item->SetTypeName( KEY_PREPREG );
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}
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else
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{
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LAYER copperLayer = Assignments.Layerdefs.Layers.at( layerBlock.ElecLayerID );
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if( layerBlockBelow.ElecLayerID.IsEmpty() )
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{
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// Dummy layer below, just use current layer to decide
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if( copperLayer.Embedding == EMBEDDING::ABOVE )
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item->SetTypeName( KEY_CORE );
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else
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item->SetTypeName( KEY_PREPREG );
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}
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else
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{
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LAYER copperLayerBelow =
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Assignments.Layerdefs.Layers.at( layerBlockBelow.ElecLayerID );
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if( copperLayer.Embedding == EMBEDDING::ABOVE )
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{
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// Need to check layer below is embedding downwards
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if( copperLayerBelow.Embedding == EMBEDDING::BELOW )
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item->SetTypeName( KEY_CORE );
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else
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item->SetTypeName( KEY_PREPREG );
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}
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else
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{
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item->SetTypeName( KEY_PREPREG );
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}
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}
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}
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int dielectricSublayer = 0;
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for( LAYER_ID constructionLaID : layerBlock.ConstructionLayers )
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{
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LAYER dielectricLayer = Assignments.Layerdefs.Layers.at( constructionLaID );
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if( dielectricSublayer )
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item->AddDielectricPrms( dielectricSublayer );
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initStackupItem( dielectricLayer, item, dielectricSublayer );
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mBoard->SetLayerName( item->GetBrdLayerId(), item->GetLayerName() );
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mLayermap.insert( { dielectricLayer.ID, item->GetBrdLayerId() } );
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++dielectricSublayer;
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}
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++stackIndex;
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}
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}
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int numElecAndPowerLayers = 0;
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for( LAYER_ID cadstarLayerID : Assignments.Layerdefs.LayerStack )
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{
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LAYER curLayer = Assignments.Layerdefs.Layers.at( cadstarLayerID );
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PCB_LAYER_ID kicadLayerID = PCB_LAYER_ID::UNDEFINED_LAYER;
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wxString layerName = curLayer.Name.Lower();
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enum class LOG_LEVEL
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{
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@ -348,14 +429,6 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup()
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}
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};
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if( prevWasDielectric && ( curLayer.Type != LAYER_TYPE::CONSTRUCTION ) )
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{
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stackup.Add( tempKiCadLayer ); //only add dielectric layers here after all are done
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dielectricSublayer = 0;
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prevWasDielectric = false;
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noOfKiCadStackupLayers++;
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}
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switch( curLayer.Type )
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||||
{
|
||||
case LAYER_TYPE::ALLDOC:
|
||||
|
|
@ -366,34 +439,15 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup()
|
|||
//Shouldn't be here if CPA file is correctly parsed and not corrupt
|
||||
THROW_IO_ERROR( wxString::Format(
|
||||
_( "Unexpected layer '%s' in layer stack." ), curLayer.Name ) );
|
||||
break;
|
||||
|
||||
case LAYER_TYPE::JUMPERLAYER:
|
||||
copperType = LAYER_T::LT_JUMPER;
|
||||
kicadLayerID = getKiCadCopperLayerID( ++numElecAndPowerLayers );
|
||||
layerTypeName = KEY_COPPER;
|
||||
break;
|
||||
|
||||
case LAYER_TYPE::ELEC:
|
||||
copperType = LAYER_T::LT_SIGNAL;
|
||||
kicadLayerID = getKiCadCopperLayerID( ++numElecAndPowerLayers );
|
||||
layerTypeName = KEY_COPPER;
|
||||
break;
|
||||
|
||||
case LAYER_TYPE::POWER:
|
||||
copperType = LAYER_T::LT_POWER;
|
||||
kicadLayerID = getKiCadCopperLayerID( ++numElecAndPowerLayers );
|
||||
layerTypeName = KEY_COPPER;
|
||||
mPowerPlaneLayers.push_back( curLayer.ID ); //we will need to add a Copper zone
|
||||
break;
|
||||
|
||||
case LAYER_TYPE::POWER:
|
||||
++numElecAndPowerLayers;
|
||||
KI_FALLTHROUGH;
|
||||
case LAYER_TYPE::CONSTRUCTION:
|
||||
kicadLayerID = PCB_LAYER_ID::UNDEFINED_LAYER;
|
||||
prevWasDielectric = true;
|
||||
layerTypeName = KEY_PREPREG;
|
||||
//TODO handle KEY_CORE and KEY_PREPREG
|
||||
//will need to look at CADSTAR layer embedding (see LAYER->Embedding) to
|
||||
//check electrical layers above and below to decide if current layer is prepreg
|
||||
// or core
|
||||
//Already dealt with these when loading board stackup
|
||||
break;
|
||||
|
||||
case LAYER_TYPE::DOC:
|
||||
|
|
@ -413,39 +467,32 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup()
|
|||
|
||||
case LAYER_SUBTYPE::LAYERSUBTYPE_NONE:
|
||||
// Generic Non-electrical layer (older CADSTAR versions).
|
||||
// Attempt to detect technical layers by string matching.
|
||||
// Attempt to detect technical layers by string matching.
|
||||
if( layerName.Contains( "glue" ) || layerName.Contains( "adhesive" ) )
|
||||
{
|
||||
wxString name = curLayer.Name.Lower();
|
||||
|
||||
if( name.Contains( "glue" ) || name.Contains( "adhesive" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Adhes, PCB_LAYER_ID::B_Adhes,
|
||||
LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( name.Contains( "silk" ) || name.Contains( "legend" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_SilkS, PCB_LAYER_ID::B_SilkS,
|
||||
LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( name.Contains( "assembly" ) || name.Contains( "fabrication" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Fab, PCB_LAYER_ID::B_Fab, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( name.Contains( "resist" ) || name.Contains( "mask" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Mask, PCB_LAYER_ID::B_Mask, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( name.Contains( "paste" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Paste, PCB_LAYER_ID::B_Paste,
|
||||
LOG_LEVEL::MSG );
|
||||
}
|
||||
else
|
||||
{
|
||||
// Does not appear to be a technical layer - warn the user.
|
||||
selectLayerID( PCB_LAYER_ID::Eco1_User, PCB_LAYER_ID::Eco2_User,
|
||||
LOG_LEVEL::WARN );
|
||||
}
|
||||
selectLayerID( PCB_LAYER_ID::F_Adhes, PCB_LAYER_ID::B_Adhes, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( layerName.Contains( "silk" ) || layerName.Contains( "legend" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_SilkS, PCB_LAYER_ID::B_SilkS, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( layerName.Contains( "assembly" ) || layerName.Contains( "fabrication" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Fab, PCB_LAYER_ID::B_Fab, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( layerName.Contains( "resist" ) || layerName.Contains( "mask" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Mask, PCB_LAYER_ID::B_Mask, LOG_LEVEL::MSG );
|
||||
}
|
||||
else if( layerName.Contains( "paste" ) )
|
||||
{
|
||||
selectLayerID( PCB_LAYER_ID::F_Paste, PCB_LAYER_ID::B_Paste, LOG_LEVEL::MSG );
|
||||
}
|
||||
else
|
||||
{
|
||||
// Does not appear to be a technical layer - Map to Eco layers for now.
|
||||
selectLayerID( PCB_LAYER_ID::Eco1_User, PCB_LAYER_ID::Eco2_User,
|
||||
LOG_LEVEL::WARN );
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -478,93 +525,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup()
|
|||
break;
|
||||
}
|
||||
|
||||
mLayermap.insert( std::make_pair( curLayer.ID, kicadLayerID ) );
|
||||
|
||||
if( dielectricSublayer == 0 )
|
||||
tempKiCadLayer = new BOARD_STACKUP_ITEM( getStackupItemType( kicadLayerID ) );
|
||||
|
||||
tempKiCadLayer->SetLayerName( curLayer.Name );
|
||||
tempKiCadLayer->SetBrdLayerId( kicadLayerID );
|
||||
|
||||
if( prevWasDielectric )
|
||||
{
|
||||
wxASSERT_MSG( kicadLayerID == PCB_LAYER_ID::UNDEFINED_LAYER,
|
||||
wxT( "Error Processing Dielectric Layer. "
|
||||
"Expected to have undefined layer type" ) );
|
||||
|
||||
if( dielectricSublayer == 0 )
|
||||
tempKiCadLayer->SetDielectricLayerId( ++numDielectricLayers );
|
||||
else
|
||||
tempKiCadLayer->AddDielectricPrms( dielectricSublayer );
|
||||
}
|
||||
|
||||
if( curLayer.MaterialId != UNDEFINED_MATERIAL_ID )
|
||||
{
|
||||
tempKiCadLayer->SetMaterial(
|
||||
cpaMaterials[curLayer.MaterialId].Name, dielectricSublayer );
|
||||
tempKiCadLayer->SetEpsilonR( cpaMaterials[curLayer.MaterialId].Permittivity.GetDouble(),
|
||||
dielectricSublayer );
|
||||
tempKiCadLayer->SetLossTangent(
|
||||
cpaMaterials[curLayer.MaterialId].LossTangent.GetDouble(), dielectricSublayer );
|
||||
//TODO add Resistivity when KiCad supports it
|
||||
}
|
||||
|
||||
tempKiCadLayer->SetThickness(
|
||||
curLayer.Thickness * KiCadUnitMultiplier, dielectricSublayer );
|
||||
|
||||
if( layerTypeName == wxEmptyString )
|
||||
layerTypeName = getLayerTypeName( kicadLayerID );
|
||||
|
||||
|
||||
if( layerTypeName != wxEmptyString )
|
||||
tempKiCadLayer->SetTypeName( layerTypeName );
|
||||
|
||||
if( !prevWasDielectric )
|
||||
{
|
||||
stackup.Add( tempKiCadLayer ); //only add non-dielectric layers here
|
||||
++noOfKiCadStackupLayers;
|
||||
layerIDs.push_back( tempKiCadLayer->GetBrdLayerId() );
|
||||
designSettings.SetEnabledLayers( LSET( &layerIDs[0], layerIDs.size() ) );
|
||||
}
|
||||
else
|
||||
++dielectricSublayer;
|
||||
|
||||
if( copperType != LAYER_T::LT_UNDEFINED )
|
||||
{
|
||||
wxASSERT( mBoard->SetLayerType( tempKiCadLayer->GetBrdLayerId(),
|
||||
copperType ) ); //move to outside, need to enable layer in board first
|
||||
lastElectricalLayerIndex = noOfKiCadStackupLayers - 1;
|
||||
wxASSERT( mBoard->SetLayerName(
|
||||
tempKiCadLayer->GetBrdLayerId(), tempKiCadLayer->GetLayerName() ) );
|
||||
//TODO set layer names for other CADSTAR layers when KiCad supports custom
|
||||
//layer names on non-copper layers
|
||||
mCopperLayers.insert( std::make_pair( curLayer.PhysicalLayer, curLayer.ID ) );
|
||||
}
|
||||
mLayermap.insert( { curLayer.ID, kicadLayerID } );
|
||||
}
|
||||
|
||||
//change last copper layer to be B_Cu instead of an inner layer
|
||||
LAYER_ID cadstarlastElecLayer = mCopperLayers.rbegin()->second;
|
||||
|
||||
PCB_LAYER_ID lastElecBrdId =
|
||||
stackup.GetStackupLayer( lastElectricalLayerIndex )->GetBrdLayerId();
|
||||
|
||||
layerIDs.erase(
|
||||
std::remove( layerIDs.begin(), layerIDs.end(), lastElecBrdId ), layerIDs.end() );
|
||||
|
||||
layerIDs.push_back( PCB_LAYER_ID::B_Cu );
|
||||
tempKiCadLayer = stackup.GetStackupLayer( lastElectricalLayerIndex );
|
||||
tempKiCadLayer->SetBrdLayerId( PCB_LAYER_ID::B_Cu );
|
||||
|
||||
wxASSERT( mBoard->SetLayerName(
|
||||
tempKiCadLayer->GetBrdLayerId(), tempKiCadLayer->GetLayerName() ) );
|
||||
|
||||
mLayermap.at( cadstarlastElecLayer ) = PCB_LAYER_ID::B_Cu;
|
||||
|
||||
//make all layers enabled and visible
|
||||
mBoard->SetEnabledLayers( LSET( &layerIDs[0], layerIDs.size() ) );
|
||||
mBoard->SetVisibleLayers( LSET( &layerIDs[0], layerIDs.size() ) );
|
||||
|
||||
mBoard->SetCopperLayerCount( numElecAndPowerLayers );
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -3169,9 +3131,9 @@ NETINFO_ITEM* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadNet( const NET_ID& aCadstarNet
|
|||
}
|
||||
|
||||
|
||||
PCB_LAYER_ID CADSTAR_PCB_ARCHIVE_LOADER::getKiCadCopperLayerID( unsigned int aLayerNum )
|
||||
PCB_LAYER_ID CADSTAR_PCB_ARCHIVE_LOADER::getKiCadCopperLayerID( unsigned int aLayerNum, bool aDetectMaxLayer )
|
||||
{
|
||||
if( aLayerNum == Assignments.Technology.MaxPhysicalLayer )
|
||||
if( aDetectMaxLayer && aLayerNum == Assignments.Technology.MaxPhysicalLayer )
|
||||
return PCB_LAYER_ID::B_Cu;
|
||||
|
||||
switch( aLayerNum )
|
||||
|
|
|
|||
|
|
@ -133,13 +133,12 @@ private:
|
|||
void loadTextVariables();
|
||||
|
||||
// Helper functions for element loading:
|
||||
BOARD_STACKUP_ITEM_TYPE getStackupItemType( const PCB_LAYER_ID& aKiCadLayer );
|
||||
wxString getLayerTypeName( const PCB_LAYER_ID& aKiCadLayer );
|
||||
|
||||
void logBoardStackupWarning( const wxString& aCadstarLayerName,
|
||||
const PCB_LAYER_ID& aKiCadLayer );
|
||||
void logBoardStackupMessage( const wxString& aCadstarLayerName,
|
||||
const PCB_LAYER_ID& aKiCadLayer );
|
||||
void initStackupItem( const LAYER& aCadstarLayer, ::BOARD_STACKUP_ITEM* aKiCadItem,
|
||||
int aDielectricSublayer );
|
||||
void loadLibraryFigures( const SYMDEF_PCB& aComponent, FOOTPRINT* aFootprint );
|
||||
void loadLibraryCoppers( const SYMDEF_PCB& aComponent, FOOTPRINT* aFootprint );
|
||||
void loadLibraryAreas( const SYMDEF_PCB& aComponent, FOOTPRINT* aFootprint );
|
||||
|
|
@ -440,9 +439,10 @@ private:
|
|||
/**
|
||||
* @brief
|
||||
* @param aLayerNum Physical / logical layer number (starts at 1)
|
||||
* @param aDetectMaxLayer If true, returns B.Cu if the requested layer is the maximum layer
|
||||
* @return PCB_LAYER_ID
|
||||
*/
|
||||
PCB_LAYER_ID getKiCadCopperLayerID( unsigned int aLayerNum );
|
||||
PCB_LAYER_ID getKiCadCopperLayerID( unsigned int aLayerNum, bool aDetectMaxLayer = true );
|
||||
|
||||
/**
|
||||
* @brief
|
||||
|
|
|
|||
Loading…
Reference in New Issue