8ccf0320b4
1) Add "rules" to base of tree for copying into BZR_HOME/rules.
...
File "rules" has instructional text as comments near top.
2) Convert all text files in repo to LF line ending form.
Any checkout done with "rules" in play will convert the working
tree to native line ending, while keeping repo as LF line ending.
2013-05-25 23:36:44 -05:00
7eb1a136f1
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions)
...
* Eeschema can generate this netlist format.
* Pcbnew can use (automatic identification) the current format or the new format.
* Cvpcb does not use yet the new format.
2012-01-26 10:37:36 +01:00
75f332aefc
Cvpcb: code cleaning. Remove not used and useless files.
2011-02-21 19:27:47 +01:00
9370dd83de
CvPcb: Code cleanup. Rename WinEDA_CvpcbFrame to CVPCB_MAINFRAME, according to coding style policy.
...
Change in CvPcb: CvPcb does not use now .dcm files, only .mod files to read modules keywords and doc
2011-02-05 17:15:48 +01:00
3c49fb1e9d
Eeschema: fix bug 706429
2011-01-23 13:32:33 +01:00
61edf74377
Demo files cleanup and update
2010-12-04 18:38:41 +01:00
485c92d4fe
Modified recent change on svn change: "PCB edge always printed when PCB edge layer not selected" was incorrect for eeschema and gerbview
...
solved bug 2070228
2008-08-25 12:28:03 +00:00
e4fdce4a47
minor update
2008-06-22 16:02:08 +00:00
dedb0228dc
add files not currently available in source (e.g. docs, modules, etc.)
...
set svn:eol-style property to native for all ascii files to support cross platform development
2007-06-05 12:10:51 +00:00
Dick Hollenbeck
jean-pierre charras
charras