Tomasz Wlostowski
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91b68e4578
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drc_proto: follow up Jeff's changes in legacy DRC/board model
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2020-07-29 23:14:03 +02:00 |
Jeff Young
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c52df811ae
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Add expression eval to constraint min/max/opt values.
Also adds error reporting for above.
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2020-07-21 23:43:10 +01:00 |
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Tomasz Wlostowski
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bc86ea7682
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drc_proto: use separate lexer for rule file from current pcbnew DRC
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2020-07-05 22:44:38 +02:00 |
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Tomasz Wlostowski
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d57d5d73b2
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qa: clearance test works and reports. about to do board outline clearance test
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2020-07-05 22:44:38 +02:00 |
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Tomasz Wlostowski
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085698d17c
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drc_proto: wip
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2020-07-05 22:44:38 +02:00 |