Commit Graph

9 Commits

Author SHA1 Message Date
Jeff Young 932fdf8674 Fix issue with default netclass vs orphaned net netclass. 2020-05-01 18:49:42 +01:00
Jeff Young f7e518dbc6 Add clearance sources to some DRC violation reports. 2020-05-01 18:49:42 +01:00
Jeff Young 41b7c62c15 Delay initialisation of global EDA_ITEMs.
It causes issues with boost::uuid generation in some versions of
boost.
2020-02-22 13:42:28 +00:00
jean-pierre charras 3fffd042de Use wxASSERT instead of assert (assert creates issues when debugging on Windows) 2019-10-20 21:19:35 +02:00
jean-pierre charras dd702cd53d Remove pads not on copper layers (just on tech layers) from connectivity calculation.
Pads not on copper layers now do not have a netname, and are no longer taken in account in connectivity.
Especially it avoid creating useless rats-nests for these pads.
2019-07-25 13:08:41 +02:00
Jeff Young 7ce38ee6f8 Performance enhancements to zone filling & track DRC.
Significant improvement in fetch time for item clearances.  On large
boards with lots of nets, maybe 10% faster zone fills and about
2x speedup on track-to-track DRC.
2019-06-25 11:34:28 +01:00
Jon Evans 1d2db311b2 Set new module parent early enough to allow pad clearance to be shown
Fixes: lp:1824587
* https://bugs.launchpad.net/kicad/+bug/1824587
2019-04-14 14:25:38 -04:00
Seth Hillbrand 4460313104 pcbnew: Separating connectivity to subdir 2018-10-12 16:31:09 -07:00
jean-pierre charras 1858852f57 rename files 2018-02-02 21:57:12 +01:00
Renamed from pcbnew/class_board_connected_item.cpp (Browse further)