Set up a new lineage for SCH_ITEMS to get back to the SCHEMATIC
they live on: Items will all be parented to the SCH_SCREEN that
they are added to, and each SCH_SCREEN will point back to the
SCHEMATIC that it is part of. Note that this hierarchy is not
the same as the actual schematic hierarchy, which continues to
be managed through SCH_SHEETs and SCH_SHEET_PATHS.
There has been a long standing (since the beginning of the project?)
issue with sharing schematics between projects. It has been somewhat
supported for complex hierarchies (a sheet shared multiple times in a
single design) but it has not been well supported for simple hierarchies
(the symbol references cannot be changed in the shared schematic). This
issue has been resolved by moving all of the symbol instance sheet paths
from the symbol definitions in the all of the project files and save all
symbol path instances in the root sheet. This ensures that orphaned
symbol instance paths do not accumulate in shared schematic files and
that designs that reuse schematic in simple hierarchies can how have
different references. It also allows the root schematic from one project
to be uses as a sub-sheet in another project.
When legacy schematics are loaded, all sheet and symbol UUIDs are
converted from time stamps to true UUIDs. This is done to ensure there
are no sheet path instance clashes between projects. That being said,
there are no checks for this. It is assumed that the probability of
UUID clashes is so low that it doesn't make sense to test for them.
The RTree does not have a deterministic iterator, so extracting items
may be in arbitrary order, causing issues as the schematic appears to
change when comparing to previous revisions.
This uses the SCH_ITEM comparison operator to for ordering by type, then
by custom sorting within type.
For the netlist, we choose the first available unit in the sheet for
each component.
Fixes#3811 | https://gitlab.com/kicad/code/kicad/issues/3811
Scope: NETLIST_ITEM, CONNECTION_TYPE, ELECTRICAL_PINTYPE,
NET_CONNECTION, NETLIST_ITEM, GRAPHIC_PINSHAPE
Note, the pin type enum had PT_ added to the front to prevent
shadowing of the INPUT symbol on msys2 (see discussion at
c17c9960d8)
Spice lines defining circuit elements are contained in a .subckt ..
.ends block. The intervening lines should be exported to the netlist as
well as the control lines.
This moves EESchema DLIST structures to rtree. These changes are more
fundamental than the pcbnew changes from 9163ac543888c01d11d1877d7c1
and 961b22d60 as eeschema operations were more dependent on passing
drawing list references around with SCH_ITEM* objects.
This change completely removes the LIB_ALIAS design pattern an replaces
it by allowing LIB_PART objects to inherit from other LIB_PART objects.
The initial implementation only allows for single inheritance and only
supports the mandatory fields in the derived part because that is all
that the current symbol library file format will support. Once the new
file format is implemented and saving to the old file format is deprecated,
more complex inheritance will be added. The LIB_ALIAS information saved
in the document files was move into the LIB_PART object. This change
impacts virtually every part of the schematic and symbol library editor
code so this commit message is woefully incomplete.
REMOVE: Removed the symbol aliases concept from the schematic and symbol
editors and the symbol viewer.
NEW: Replace the symbol alias concept with simple inheritance that allows
a library symbol to be derived from another library symbol.
The pin name defined in Eeschema is now available as pad info.
Useful for the board designer (the pin function is displayed in the message panel).
Needed for the Gerber P&P files.
This reverts commit eadf6d93bc.
because the issue with net names containing '/' is not actually inside the netlist.
This commit eadf creates issues with ngspice 2.8 and older, and do not fix anything in ngspice
Netlists do not accept any char in netnames (especially spice).
They must use only "/" as root sheet path name.
Especially _( "<root sheet>" ) breaks netlists because:
- there is a space in name, and special chars (< and >)
- it is a translatable name. so the actual name cannot be managed.
- most of netlist code in Kicad expects a "/" as root path.
Net names in eeschema that include '/' are escaped ('/' replaced by "{slash}")
Escaped netnames are only for internal use, and must be unescaped in spice netlist and dialogs.
Bus upgrades: core new connectivity code
Bus upgrades: eeschema integration and modifications
Bus upgrades: eeschema dialogs
Bus upgrades: netlist export
Bus upgrades: file format changes
This breaks the following functions out to a general-purposed refdes utils
header:
* MODULE::GetReferencePrefix()
* kicad_string.h RefDesStringCompare()
This acheives:
* Slimming of MODULE interface
* Placement of refdes code in common rather than pcbnew
** Testing of this code in qa_common
* Tighter and smaller includes for code that only needed refdes functions
Note: there are failing tests commited (as expected failures). These
are the cause of lp:1813669 and will be fixed as a follow-up commit.
Spice may include a list of directives that are wrapped with
.control and .endc. Such directives do not have a dot prefix, so
they need to be handled in a special way.
Fixes: lp:1787902
* https://bugs.launchpad.net/kicad/+bug/1787902
The old item pointers (which aren't safe to keep around) were
removed in favour of opaque references (void*) which are then
compared against existing items when needed.
Also improves brightening by brightening the whole footprint
(ie: its pads, drawings, reference and value) rather than just
its target cross.
(cherry picked from commit 30e90b0)
Also hooks up the Python netlist reader to the descriptions so
that they appear correctly in BOMs. (The BOM generators used
to always get the root component's description rather than the
alias's description.)
Fixes: lp:1774358
* https://bugs.launchpad.net/kicad/+bug/1774358