Commit Graph

769 Commits

Author SHA1 Message Date
qu1ck 0c049eccc7 Fix a bunch of compiler warnings 2023-04-11 17:01:30 +00:00
jean-pierre charras 4d05bd62da drc_test_provider_library_parity: fix false positive.
After last changes in PCB_SHAPES, there were issues when comparing coordinates
of shapes.
Use now a footprint not flipped, not rotated and at position 0,0 for comparisons.
Fixes #14496
https://gitlab.com/kicad/code/kicad/issues/14496
2023-04-05 18:25:19 +02:00
Jeff Young fd07f50c44 Report collisions of items with nets as SHORTING, not CLEARANCE.
Fixes https://gitlab.com/kicad/code/kicad/issues/14312
2023-04-02 21:07:52 +01:00
Jeff Young 28028c941e Retire Local/Draw coords distinction from PAD (the last object to have it). 2023-04-02 18:02:41 +01:00
Jeff Young bbd6c80507 Collapse FP_* down into their PCB_* equivalents. 2023-03-31 22:57:46 +01:00
Jeff Young a214ac0310 Better reporting of copper <--> keepout area clearances.
(Keepout areas can keep-out copper, but they don't have a clearance
to copper.)

Fixes https://gitlab.com/kicad/code/kicad/issues/14375
2023-03-26 20:57:59 +01:00
Jeff Young 9976b9ce8c Only report on clearances where there was one defined.
If it's 0, it's just a straight-up collision.
2023-03-26 20:46:59 +01:00
Jeff Young 0266d03f79 Run SILK_CLEARANCE rules on mask layer when testing silk-to-mask clearance.
This allows custom rules to be authored without firing the auto-generated
rule from Board Setup > Silk Item Clearance (which should be only for silk-
to-silk clearances).

Fixes https://gitlab.com/kicad/code/kicad/issues/14417
2023-03-26 20:42:41 +01:00
Jeff Young 04f6f04bed Test silk/mask collisions on the correct layer.
Fixes https://gitlab.com/kicad/code/kicad/issues/14417
2023-03-26 16:27:05 +01:00
Jeff Young c5e66361db Allow solder mask bridges between net-tie-group pads.
Fixes https://gitlab.com/kicad/code/kicad/issues/14412
2023-03-25 16:11:07 +00:00
Jeff Young d6dd58fff9 Keep track of single-pad-islands so we can discount spokes to them. 2023-03-25 10:44:46 +00:00
Seth Hillbrand 914b5a4d21 Simplify test for substantial nubs
Substantial elements following a divot should be at least as far in each
cardinal direction from the origin point in order to be considered
substantial.  This catches cases where the "substantial" element is
actually a straight segment away from the divot

Fixes https://gitlab.com/kicad/code/kicad/issues/14130
2023-03-22 13:01:50 -07:00
Jeff Young 129ccb891e Use standard paradigm for macro scope limiting. 2023-03-19 20:43:18 +00:00
Jeff Young ee1d9c561c Improve zone & rule area reporting.
Also removes a bunch of "wxEmptyString" where it was degrading readability.

Also fixes a bug where footprint zones were getting sorted incorrectly
due to rotation of coordinates.

Fixes https://gitlab.com/kicad/code/kicad/issues/14322
2023-03-17 13:28:29 +00:00
Jeff Young 967ee2c85b Improved macro protection. 2023-03-17 11:04:58 +00:00
Jeff Young 5427100539 Handle plotting of text on solder mask layer.
Admittedly this is an odd thing to do, but we should still be internally
consistent, and it has come up in customers' files.

Fixes https://gitlab.com/kicad/code/kicad/issues/14226
2023-03-12 21:21:15 +00:00
jean-pierre charras e6945a85b0 fix compil and Coverity warnings. 2023-03-12 15:19:50 +01:00
jean-pierre charras a264608368 drc_test_provider_library_parity.cpp: fix a typo that crashes Pcbnew. 2023-03-11 15:01:26 +01:00
Jeff Young 357427d803 Graphical diff for board vs library footprints.
Fixes https://gitlab.com/kicad/code/kicad/issues/13736
2023-03-10 17:16:40 +00:00
Jeff Young 2d6ab62da4 ADDED: schematic/library diff for symbols. 2023-03-09 18:04:52 +00:00
Seth Hillbrand 6b4c366cb8 Cleanup DRC check for via layers
Vias should only be placed on the layers through which they pass.  if
they pass through front or back copper, then they also pass through the
tech layers on that side

This is an update to 9d3f4bef6a
2023-03-07 11:13:05 -08:00
Jeff Young 33e7c78533 Edge connectors shouldn't trigger edge clearance violations.
Fixes https://gitlab.com/kicad/code/kicad/issues/14199
2023-03-07 12:23:18 +00:00
jean-pierre charras e7c3350482 fix compil warnings 2023-03-07 09:52:29 +01:00
Seth Hillbrand 7653a2bf99 Smarten connection width checker looking for splits
Fractured polygons are always fractured along the x-axis, so when
checking to see if a segment is a fracture point, we check if the y
coordinate is equal.  This avoids situations where there are multiple
fracture points between two inflection points

Additionally, we add a second check to ensure we don't hit spurious
blobs (all kinks should be symmetric and therefore be substantial in
each direction)

Fixes https://gitlab.com/kicad/code/kicad/issues/14130
2023-03-06 16:14:34 -08:00
Jeff Young 25623552f6 ADDED: board/library inspection for footprint differences.
Fixes https://gitlab.com/kicad/code/kicad/issues/13736
2023-03-06 23:08:59 +00:00
Wayne Stambaugh a1fb8e1b1d Coverity fixes and code cleaning. 2023-03-06 07:12:18 -05:00
Seth Hillbrand f24deac017 Consider oblong holes with x/y equal size as drills
An oblong hole with drillsizex = drillsizey is the same as a circular
drill hit and should be converted to such in outputs (both excellon and
DRC)
2023-03-03 00:42:44 +01:00
Seth Hillbrand 597ef81e53 Allow micro/buried via holes to be considered
hole_to_hole clearance should account for all holes in the board.
Previously, we had excluded non through holes from this test but that
omits via holes that can still foul a future drill hit.

Designers wanting the old behavior can explicitly set the hole_to_hole
clearance to 0mm for specific ViaType pairs
2023-03-03 00:42:44 +01:00
Wayne Stambaugh 789bf6455a Coverity fixes and code cleaning. 2023-03-02 09:04:47 -05:00
Seth Hillbrand a0f99ea8ba Allow for rounding error in connection width checker
We perform checks using squared distance but this loses the integer
rounding in the standard norm.  To correct for this, we allow a single
IU in the restriction, allowing fractionally smaller connection widths
before calculating the squared limit

Fixes https://gitlab.com/kicad/code/kicad/issues/14130

Fixes https://gitlab.com/kicad/code/kicad/issues/14131
2023-02-28 15:26:16 -08:00
Jeff Young 7bb2cdd658 Better error reporting for constraints (and a bug fix for no constraints).
Fixes https://gitlab.com/kicad/code/kicad/issues/14070
2023-02-28 18:07:29 +00:00
jean-pierre charras 7256a51e8e Fixes in build board outlines as polygon and convert_shape_list_to_polygon:
- Ensure Bezier curves have their polygon build before use it.
- When building board outlines as polygon the same chaining epsilon value
for DRC, export step and 3D view (default 0.01mm).
Fixes #14115
https://gitlab.com/kicad/code/kicad/issues/14115
Fixes #14009
https://gitlab.com/kicad/code/kicad/issues/14009
2023-02-28 16:45:03 +01:00
Jon Evans 8440d7258b Do not invalidate board caches during DRC
Footprints now modify their parent container when destroyed due to
26542796, and a temporary footprint is created during DRC
in some situations.  This can lead to board caches being messed
with during DRC which can cause unpredictable bad effects due to
multithreading.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/13844
2023-02-24 22:55:32 -05:00
Jeff Young d9a77e6a64 Add DRCEpsilon to net-tie-exclusion testing.
Fixes https://gitlab.com/kicad/code/kicad/issues/14008
2023-02-24 12:44:55 +00:00
Marek Roszko aacc9746e3 Yeet the last of wxSize/wxPoint to stop leaking gdicmn everywhere 2023-02-18 22:57:18 -05:00
Jeff Young 5b0f1376c0 Simplify code now that we no longer drop out on first rule fired. 2023-02-16 17:55:33 +00:00
Jeff Young 978c2b074e Negative clearance means test will be ignored, not rule. 2023-02-16 17:39:47 +00:00
Jeff Young 407cdd63fb Translatable strings. 2023-02-16 17:28:06 +00:00
Seth Hillbrand 9d3f4bef6a DRC: Verify overlapping layers in physical clearance
When checking the physical clearance on a layer, it is critical to check
that the via hole exists on that layer.  Blind/buried and micro vias may
not overlap, so should be excluded from this check when they don't exist
on a particular layer

Similarly, we should only be reporting a single physical clearance error
for each item pair even though they may have multiple errors across
multiple layers in the case of via-via clearance
2023-02-15 11:35:24 -08:00
Seth Hillbrand e7fe69b97f Better handling of vertex sorting
Nominally, the zcode of a vertex is unique.  This is not 100% true,
however, as we must interlace two 32-bit numbers into a single 32-bit
number.  Sorting needs to account for the possibility that the zcode
will be the same while other elements of the vertex are different.  This
commit fixes the broken boolean logic to more clearly handle these cases

Fixes https://gitlab.com/kicad/code/kicad/issues/13867
2023-02-13 11:21:04 -08:00
Seth Hillbrand 90a388571e Fix copy-pasta
testing 'othervia' for dynamic_cast success needs to use `othervia`
rather than `via` which might still be null

Fixes Sentry issue KICAD-5K
2023-02-10 13:33:21 -08:00
Jeff Young a59c1afa53 Fix two bugs in RTree polygon collions special case.
1) Special case doesn't work for polygons with holes
2) Fix special case to handle intersecting lines where neither end is
   in the polygon.

Note that only (1) is required for the bug below.  (2) was just
discovered while implementing (1).

Fixes https://gitlab.com/kicad/code/kicad/issues/13779
2023-02-04 13:46:40 +00:00
Jeff Young 8ecf64b6c5 Don't run DRC rules on non-existant layers.
Fixes https://gitlab.com/kicad/code/kicad/issues/13753
2023-02-03 15:08:31 +00:00
Jeff Young 235925d62c Clearer reporting of negative clearances. 2023-02-03 15:08:31 +00:00
Jon Evans 26b9d2f5ac DRC: Allow disabling DP constraints in specific areas
Fixes https://gitlab.com/kicad/code/kicad/-/issues/13743
2023-02-01 23:11:39 -05:00
Jeff Young 50e9685490 Check for tented vias before expanding solder mask.
Fixes https://gitlab.com/kicad/code/kicad/issues/13705
2023-01-30 17:56:35 +00:00
Jeff Young e886ccacbd Cleanup unused local variable. 2023-01-24 23:45:55 +00:00
Jeff Young 00e2bbac5a Special-case net-ties for solder mask bridging.
Fixes https://gitlab.com/kicad/code/kicad/issues/13646
2023-01-24 11:33:08 +00:00
Jon Evans 12b0a12d74 Handle DP checks for board minimum rules
Fixes https://gitlab.com/kicad/code/kicad/-/issues/13640
2023-01-23 17:45:16 -05:00
Jeff Young ece775c53c Blind/buried vias are drilled, and drilled holes need to avoid prior-burned holes.
Fixes https://gitlab.com/kicad/code/kicad/issues/13627
2023-01-23 16:25:29 +00:00