Includes:
- Fix GAL to draw closed polygons in eeschema
- Add functionality to eeschema to draw arbitary polygons
- Update polygon item previews to have customisable edge colour
- Add new SCH_RULE_AREA class, derived from a poly SCH_SHAPE
- Add SCH_RULE_AREA to paint and plot methods
- Add new rule area color preference to themes
Also fixes a bug where ERC testing for text variables in sheet pins
would start with the wrong sheet.
Also fixes a bug where ERC testing of similar labels would use the
wrong sheet.
Also fixes a bug where ERC testing of bus-to-net conflicts would use
the wrong sheet.
Also fixes a bug where ERC didn't process variable references when
checking hierarchical labels against sheet pins.
Also fixes a bug where ERC multiple-drivers and netclass-conflicts
tests didn't set a sheetpath.
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
Reports a warning (by default) for missing units
Reports an error for missing units with power input pins
Reports a warning for missing units with input pins
Reports a warning for missing units with bidi pins
Fixes https://gitlab.com/kicad/code/kicad/issues/1922
1) Make sure we set an absolute path on the sheet.
2) Don't mix RTree iterators; wires get skipped between buses.
3) Implement a real ERC error so we don't assert.
Fixes https://gitlab.com/kicad/code/kicad/issues/7042
Input pins can be driven by many pin types: output, passive, 3state, I/O
But Power pins can be driven by only power output pins, and cannot
use the same criteria in ERC tests.
Error codes can shift around if the enum ordering is
not maintained, which is more fragile than the settings
key which should never be changed after a new code is
created.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/6001
James J
Jeff Young
Roberto Fernandez Bautista
jean-pierre charras
Marek Roszko
Seth Hillbrand
Graham Keeth
Jon Evans
Wayne Stambaugh
Ian McInerney
Tomasz Wlostowski