C++20 added new reverse and rewritten candidates. This can confuse the compiler because it'll test both A==B and B==A for overloads.
Because we were defining parent class equality overloads, A==B and B==A was considered ambigious due to both being compatible in casting.
So we needed to add explicit child class equality operator overloads
Prior to this change, the schematic connectivity was updated any time a
change was made to a connectable object. Now the connectivity is only
updated when an object change actually affects the connectivity. Other
properties like line width, fill type, custom fonts, etc. will not cause
the connectivity graph to be rebuilt.
The SCH_COMMIT flag SKIP_CONNECTIVITY has been removed. All schematic
objects can test if they are connectable and if there have been changes
to any connection properties that require a connectivity rebuild.
Remove duplicate rebuild connectivity calls from editor control tool.
This was causing the tangling end test to get called four times on every
undo and redo action because the dangling end test is already called in
the connectivity graph calculation code.
Update connectivity when changing label names which fixes an unreported
connectivity bug.
This has now pushed the issue down to a broken RTree issue. Skipping the
asserts in debug builds will still crash but now it's pushed down to the
RTree.
A sheetpath is required to correctly resolve text variables.
Depending on currentSheet is rife with bugs.
There are many places where we do *not* want to be prepending
field names to the field values, such as netlisting,
building PDF hypertext menus, etc.
Also, Find/Replace needs to work on unresolved text, as
that's what we're going to display (and if replace nuked
your variable references you wouldn't be happy).
- Consistent calculation of IsStacked() for pins across ERC checks
- Correct placement of ERC marker for unresolved field variables
- Add sheet-specific paths to two ERC check results
Same pin name != same net name unless the pins are explicitly connected
Also add pin number to all unconnected pads ensuring they have unique
nets
Fixes https://gitlab.com/kicad/code/kicad/issues/13236
ba7a06f5 tried to fix a (minor) issue in net names when the name was coming
from a input power pin having a '/' in name. But ba7a06f5 blindly escaped any '/'
in net name, and the hierarchy info was lost.
Now only the pin name is escaped (like any other pin name used in net names)
m_layer was not re-initialized in CTOR, so it was the default value (LAYER_WIRE)
This is incorrect for a pin, and can create errors in some functions (like IsType() )
Fixes#1818https://gitlab.com/kicad/code/kicad/issues/1818
Marek Roszko
Jeff Young
Wayne Stambaugh
Alex Shvartzkop
Seth Hillbrand
Jon Evans
Mike Williams
James J
jean-pierre charras