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5 Commits

Author SHA1 Message Date
Jeff Young 096e342386 Prefix TRACK, ARC and VIA. 2021-06-11 22:07:02 +01:00
Marek Roszko 10e60acf34 Clean up including of board_design_settings.h 2021-06-06 15:03:42 -04:00
Ian McInerney 4f05262705 Cleanup includes in board.h and footprint.h 2021-06-03 20:19:52 +01:00
Jeff Young 00ed75b891 Fix DRC performance with multi-layer keepout zones. 
The main issue was a parameter mismatch which caused On^2 behaviour
for zone layers.

But there are several other performance optimizations here, along
with status bar updating for zones while running the dissallow test.

Fixes https://gitlab.com/kicad/code/kicad/issues/8521
 2021-06-02 14:11:43 +01:00
Jeff Young 4c3d78dec0 Break out separate holes-co-located violation. 
Fixes https://gitlab.com/kicad/code/kicad/issues/8456
 2021-05-20 10:36:56 +01:00
Renamed from pcbnew/drc/drc_test_provider_hole_clearance.cpp (Browse further)