f95cceeff0
Update demos
2018-01-12 21:30:07 +01:00
419c6e198e
Update interf_u demo to use latest libraries and the new sym-lib-table
2017-11-14 17:16:23 +01:00
75b1df464d
Pcbnew and Gerbview: layer manager: use double click to edit color (as usual to edit someting) and simple click (as previously) to select the layer. Reason: avoid opening the color dialog each time a new layer is selected.
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Update interf_u demo to use recent library components..
2016-01-28 09:02:25 +01:00
6bae852cb9
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export.
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dialog_fp_lib_table: remember during a session the last open table (global or local).
drawing_tool: fix compil warning
Update demos.
2014-09-22 09:51:06 +02:00
4428d69a63
Pcbnew: Fix a bug when reading a netlist which forces pcbnew to read lib files to find a footprint even if the right footprint is already loaded (which explains the long time to load netlists)
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Netlist dialog: add option to report only most important messages. Useful for large boards.
class REPORTER: add features to allow a basic message filtering (flags to report all/warning/error messages)
Fix Bug #1214599 ( tools are deselected on Move command )
2013-08-23 08:38:57 +02:00
8ccf0320b4
1) Add "rules" to base of tree for copying into BZR_HOME/rules.
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File "rules" has instructional text as comments near top.
2) Convert all text files in repo to LF line ending form.
Any checkout done with "rules" in play will convert the working
tree to native line ending, while keeping repo as LF line ending.
2013-05-25 23:36:44 -05:00
7eb1a136f1
Pcbnew: First draft to use a new netlist format ( containing the same info as the intermediate netlist, but using S expressions)
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* Eeschema can generate this netlist format.
* Pcbnew can use (automatic identification) the current format or the new format.
* Cvpcb does not use yet the new format.
2012-01-26 10:37:36 +01:00
75f332aefc
Cvpcb: code cleaning. Remove not used and useless files.
2011-02-21 19:27:47 +01:00
9370dd83de
CvPcb: Code cleanup. Rename WinEDA_CvpcbFrame to CVPCB_MAINFRAME, according to coding style policy.
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Change in CvPcb: CvPcb does not use now .dcm files, only .mod files to read modules keywords and doc
2011-02-05 17:15:48 +01:00
3c49fb1e9d
Eeschema: fix bug 706429
2011-01-23 13:32:33 +01:00
61edf74377
Demo files cleanup and update
2010-12-04 18:38:41 +01:00
485c92d4fe
Modified recent change on svn change: "PCB edge always printed when PCB edge layer not selected" was incorrect for eeschema and gerbview
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solved bug 2070228
2008-08-25 12:28:03 +00:00
e4fdce4a47
minor update
2008-06-22 16:02:08 +00:00
dedb0228dc
add files not currently available in source (e.g. docs, modules, etc.)
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set svn:eol-style property to native for all ascii files to support cross platform development
2007-06-05 12:10:51 +00:00
jean-pierre charras
Dick Hollenbeck
charras