kicad

11,574 Commits 9 Branches 105 Tags 1.3 GiB

Author	SHA1	Message	Date
jean-pierre charras	353e91a6f8	Update demos	2017-11-21 21:26:06 +01:00
jean-pierre charras	fe919cd456	Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .	2014-01-07 20:42:34 +01:00
Dick Hollenbeck	8ccf0320b4	1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending.	2013-05-25 23:36:44 -05:00
jean-pierre charras	0cb6cd8c02	Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy. Known bug in intermediate netlist generation: multi parts per package have their common pins listed more than once in nets section. Will be fixed.	2011-02-10 09:27:36 +01:00
jean-pierre charras	792eb943b5	fixed bug 583939	2010-05-23 19:39:47 +02:00

Renamed from demos/sonde xilinx/sonde xilinx.cache.lib (Browse further)