* Use a regular expression to enforce more stringent bus label testing.
* Add validator to edit label dialog to prevent space character from being
used in labels.
* Move the hierarchical label connected test into the NETLIST_OBJECT class.
* ERC pin type strings can now be translated.
* Remove unused EDA_DRAW_PANEL attribute from all ERC test functions.
* Add get marker count method to SCH_SCREENS object.
* Redundant header removal.
* Lots of coding style policy fixes.
* Fix bug that prevented component from being replaced in library when
the component root name was changed.
* Fix drawing bug when changing text or field item string while move in
progress.
* Fix drawing bug when rotating text item while move in progress.
* Prevent undo or redo when editing a component draw item.
* Fix assert bug when replacing component in library when the component
root name was changed.
* Fix bug in field editor caused by new root alias implementation that
prevented any field from being changed.
* Fix minor spacing issues with EESchema find dialog.
* Deprecate remaining internal linked list code from component library
objects.
* Rename pin object files to match new library object file naming
scheme.
* Move LIB_TEXT object definition into it's own header file.
* Continue component library class clean up and encapsulation work.
* Change hierarchical sheet label container to boost::vector_ptr.
* Encapsulate hierarchical label handling in hierarchical sheet class.
* Convert some missed occurrences of wxString::GetData() to GetChars( wxString ).
* Fix some minor code formatting issues.
In netlist generation, changed the rule to calculate netnames of nets with labels:
Previously, named nets (i.e. nets with local, hierarchical or global labels) have their name
defined by the first label found in list.
So net names could be changed without really changing the schematic.
Now the names are calculated from the rules (by priority order) :
1 - use the most top level labels in hierarchies.
2 - use global labels first, local labels next (hidden power pins names are global labels).
3 - use alphabetic sort (so, if GND and AGND are connected, the net will be always named AGND,
and adding a VSS connection cannot change the net name)
So power nets and nets that have more than one label cannot have their netname changed
if there is no actual change relative to these nets names in schematic
* Complete comment translation for all EESchema source files.
* Complete comment translation for all 3D viewer source files.
* Rename class class_hierarchical_PIN_sheet to SCH_SHEET_PIN.
* Rename class DrawSheetStruct to SCH_SHEET.
* Tool tip capitalization fixes.
* Uncrustify and spell check comments and strings in all modified source
files.
Wayne Stambaugh
Dick Hollenbeck
jean-pierre charras
stambaughw