992 lines
28 KiB
C++
992 lines
28 KiB
C++
/*
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* This program source code file is part of KICAD, a free EDA CAD application.
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*
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* Copyright (C) 2017 CERN
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* Copyright (C) 2018-2022 KiCad Developers, see AUTHORS.txt for contributors.
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* @author Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifdef PROFILE
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#include <profile.h>
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#endif
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#include <algorithm>
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#include <future>
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#include <initializer_list>
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#include <connectivity/connectivity_data.h>
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#include <connectivity/connectivity_algo.h>
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#include <connectivity/from_to_cache.h>
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#include <project/net_settings.h>
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#include <board_design_settings.h>
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#include <geometry/shape_segment.h>
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#include <geometry/shape_circle.h>
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#include <ratsnest/ratsnest_data.h>
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#include <progress_reporter.h>
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#include <thread_pool.h>
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#include <trigo.h>
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#include <drc/drc_rtree.h>
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CONNECTIVITY_DATA::CONNECTIVITY_DATA()
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{
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m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
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m_progressReporter = nullptr;
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m_fromToCache.reset( new FROM_TO_CACHE );
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}
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CONNECTIVITY_DATA::CONNECTIVITY_DATA( const std::vector<BOARD_ITEM*>& aItems, bool aSkipRatsnest )
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: m_skipRatsnest( aSkipRatsnest )
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{
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Build( aItems );
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m_progressReporter = nullptr;
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m_fromToCache.reset( new FROM_TO_CACHE );
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}
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CONNECTIVITY_DATA::~CONNECTIVITY_DATA()
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{
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Clear();
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}
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bool CONNECTIVITY_DATA::Add( BOARD_ITEM* aItem )
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{
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m_connAlgo->Add( aItem );
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return true;
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}
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bool CONNECTIVITY_DATA::Remove( BOARD_ITEM* aItem )
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{
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m_connAlgo->Remove( aItem );
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return true;
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}
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bool CONNECTIVITY_DATA::Update( BOARD_ITEM* aItem )
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{
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m_connAlgo->Remove( aItem );
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m_connAlgo->Add( aItem );
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return true;
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}
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void CONNECTIVITY_DATA::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter )
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{
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aBoard->CacheTriangulation( aReporter );
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std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
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if( !lock )
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return;
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if( aReporter )
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{
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aReporter->Report( _( "Updating nets..." ) );
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aReporter->KeepRefreshing( false );
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}
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std::shared_ptr<NET_SETTINGS>& netSettings = aBoard->GetDesignSettings().m_NetSettings;
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m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
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m_connAlgo->Build( aBoard, aReporter );
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m_netclassMap.clear();
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for( NETINFO_ITEM* net : aBoard->GetNetInfo() )
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{
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net->SetNetClass( netSettings->GetEffectiveNetClass( net->GetNetname() ) );
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if( net->GetNetClass()->GetName() != NETCLASS::Default )
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m_netclassMap[ net->GetNetCode() ] = net->GetNetClass()->GetName();
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}
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if( aReporter )
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{
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aReporter->SetCurrentProgress( 0.75 );
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aReporter->KeepRefreshing( false );
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}
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RecalculateRatsnest();
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if( aReporter )
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{
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aReporter->SetCurrentProgress( 1.0 );
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aReporter->KeepRefreshing( false );
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}
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}
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void CONNECTIVITY_DATA::Build( const std::vector<BOARD_ITEM*>& aItems )
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{
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std::unique_lock<KISPINLOCK> lock( m_lock, std::try_to_lock );
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if( !lock )
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return;
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m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
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m_connAlgo->LocalBuild( aItems );
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RecalculateRatsnest();
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}
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void CONNECTIVITY_DATA::Move( const VECTOR2I& aDelta )
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{
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m_connAlgo->ForEachAnchor( [&aDelta]( CN_ANCHOR& anchor )
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{
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anchor.Move( aDelta );
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} );
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}
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void CONNECTIVITY_DATA::updateRatsnest()
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{
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#ifdef PROFILE
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PROF_TIMER rnUpdate( "update-ratsnest" );
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#endif
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std::vector<RN_NET*> dirty_nets;
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// Start with net 1 as net 0 is reserved for not-connected
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// Nets without nodes are also ignored
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std::copy_if( m_nets.begin() + 1, m_nets.end(), std::back_inserter( dirty_nets ),
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[] ( RN_NET* aNet )
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{
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return aNet->IsDirty() && aNet->GetNodeCount() > 0;
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} );
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GetKiCadThreadPool().parallelize_loop( 0, dirty_nets.size(),
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[&]( const int a, const int b)
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{
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for( int ii = a; ii < b; ++ii )
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dirty_nets[ii]->Update();
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}).wait();
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#ifdef PROFILE
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rnUpdate.Show();
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#endif
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}
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void CONNECTIVITY_DATA::addRatsnestCluster( const std::shared_ptr<CN_CLUSTER>& aCluster )
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{
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RN_NET* rnNet = m_nets[ aCluster->OriginNet() ];
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rnNet->AddCluster( aCluster );
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}
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void CONNECTIVITY_DATA::RecalculateRatsnest( BOARD_COMMIT* aCommit )
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{
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m_connAlgo->PropagateNets( aCommit );
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int lastNet = m_connAlgo->NetCount();
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if( lastNet >= (int) m_nets.size() )
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{
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unsigned int prevSize = m_nets.size();
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m_nets.resize( lastNet + 1 );
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for( unsigned int i = prevSize; i < m_nets.size(); i++ )
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m_nets[i] = new RN_NET;
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}
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else
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{
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for( size_t ii = lastNet; ii < m_nets.size(); ++ii )
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m_nets[ii]->Clear();
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}
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const std::vector<std::shared_ptr<CN_CLUSTER>>& clusters = m_connAlgo->GetClusters();
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int dirtyNets = 0;
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for( int net = 0; net < lastNet; net++ )
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{
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if( m_connAlgo->IsNetDirty( net ) )
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{
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m_nets[net]->Clear();
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dirtyNets++;
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}
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}
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for( const std::shared_ptr<CN_CLUSTER>& c : clusters )
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{
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int net = c->OriginNet();
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// Don't add intentionally-kept zone islands to the ratsnest
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if( c->IsOrphaned() && c->Size() == 1 )
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{
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if( dynamic_cast<CN_ZONE_LAYER*>( *c->begin() ) )
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continue;
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}
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if( m_connAlgo->IsNetDirty( net ) )
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addRatsnestCluster( c );
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}
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m_connAlgo->ClearDirtyFlags();
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if( !m_skipRatsnest )
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updateRatsnest();
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}
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void CONNECTIVITY_DATA::BlockRatsnestItems( const std::vector<BOARD_ITEM*>& aItems )
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{
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std::vector<BOARD_CONNECTED_ITEM*> citems;
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for( BOARD_ITEM* item : aItems )
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{
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if( item->Type() == PCB_FOOTPRINT_T )
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{
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for( PAD* pad : static_cast<FOOTPRINT*>(item)->Pads() )
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citems.push_back( pad );
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}
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else
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{
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if( BOARD_CONNECTED_ITEM* citem = dynamic_cast<BOARD_CONNECTED_ITEM*>( item ) )
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citems.push_back( citem );
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}
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}
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for( const BOARD_CONNECTED_ITEM* item : citems )
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{
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if ( m_connAlgo->ItemExists( item ) )
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{
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CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( item );
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for( CN_ITEM* cnItem : entry.GetItems() )
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{
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for( const std::shared_ptr<CN_ANCHOR>& anchor : cnItem->Anchors() )
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anchor->SetNoLine( true );
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}
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}
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}
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}
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int CONNECTIVITY_DATA::GetNetCount() const
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{
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return m_connAlgo->NetCount();
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}
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void CONNECTIVITY_DATA::FindIsolatedCopperIslands( ZONE* aZone, std::vector<int>& aIslands )
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{
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// TODO(JE) ZONES
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#if 0
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m_connAlgo->FindIsolatedCopperIslands( aZone, aIslands );
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#endif
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}
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void CONNECTIVITY_DATA::FindIsolatedCopperIslands( std::vector<CN_ZONE_ISOLATED_ISLAND_LIST>& aZones,
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bool aConnectivityAlreadyRebuilt )
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{
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m_connAlgo->FindIsolatedCopperIslands( aZones, aConnectivityAlreadyRebuilt );
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}
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void CONNECTIVITY_DATA::ComputeLocalRatsnest( const std::vector<BOARD_ITEM*>& aItems,
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const CONNECTIVITY_DATA* aDynamicData,
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VECTOR2I aInternalOffset )
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{
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if( !aDynamicData )
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return;
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m_dynamicRatsnest.clear();
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std::mutex dynamic_ratsnest_mutex;
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// This gets connections between the stationary board and the
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// moving selection
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auto update_lambda = [&]( int nc )
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{
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RN_NET* dynamicNet = aDynamicData->m_nets[nc];
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RN_NET* staticNet = m_nets[nc];
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/// We don't need to compute the dynamic ratsnest in two cases:
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/// 1) We are not moving any net elements
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/// 2) We are moving all net elements
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if( dynamicNet->GetNodeCount() != 0
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&& dynamicNet->GetNodeCount() != staticNet->GetNodeCount() )
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{
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VECTOR2I pos1, pos2;
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if( staticNet->NearestBicoloredPair( dynamicNet, pos1, pos2 ) )
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{
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RN_DYNAMIC_LINE l;
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l.a = pos1;
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l.b = pos2;
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l.netCode = nc;
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std::lock_guard<std::mutex> lock( dynamic_ratsnest_mutex );
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m_dynamicRatsnest.push_back( l );
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}
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}
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};
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GetKiCadThreadPool().parallelize_loop( 1, aDynamicData->m_nets.size(),
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[&]( const int a, const int b)
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{
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for( int ii = a; ii < b; ++ii )
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update_lambda( ii );
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}).wait();
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// This gets the ratsnest for internal connections in the moving set
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const std::vector<CN_EDGE>& edges = GetRatsnestForItems( aItems );
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for( const CN_EDGE& edge : edges )
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{
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const std::shared_ptr<CN_ANCHOR>& nodeA = edge.GetSourceNode();
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const std::shared_ptr<CN_ANCHOR>& nodeB = edge.GetTargetNode();
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RN_DYNAMIC_LINE l;
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// Use the parents' positions
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l.a = nodeA->Parent()->GetPosition() + aInternalOffset;
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l.b = nodeB->Parent()->GetPosition() + aInternalOffset;
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l.netCode = 0;
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m_dynamicRatsnest.push_back( l );
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}
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}
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void CONNECTIVITY_DATA::ClearLocalRatsnest()
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{
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m_connAlgo->ForEachAnchor( []( CN_ANCHOR& anchor )
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{
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anchor.SetNoLine( false );
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} );
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HideLocalRatsnest();
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}
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void CONNECTIVITY_DATA::HideLocalRatsnest()
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{
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m_dynamicRatsnest.clear();
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}
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void CONNECTIVITY_DATA::PropagateNets( BOARD_COMMIT* aCommit, PROPAGATE_MODE aMode )
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{
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m_connAlgo->PropagateNets( aCommit, aMode );
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}
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bool CONNECTIVITY_DATA::IsConnectedOnLayer( const BOARD_CONNECTED_ITEM *aItem, int aLayer,
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const std::initializer_list<KICAD_T>& aTypes,
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bool aCheckOptionalFlashing ) const
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{
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CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY &entry = m_connAlgo->ItemEntry( aItem );
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auto matchType =
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[&]( KICAD_T aItemType )
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{
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if( aTypes.size() == 0 )
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return true;
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return alg::contains( aTypes, aItemType);
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};
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for( CN_ITEM* citem : entry.GetItems() )
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{
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for( CN_ITEM* connected : citem->ConnectedItems() )
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{
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CN_ZONE_LAYER* zoneLayer = dynamic_cast<CN_ZONE_LAYER*>( connected );
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if( connected->Valid()
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&& connected->Layers().Overlaps( aLayer )
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&& matchType( connected->Parent()->Type() )
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&& connected->Net() == aItem->GetNetCode() )
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{
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if( aItem->Type() == PCB_PAD_T && zoneLayer )
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{
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const PAD* pad = static_cast<const PAD*>( aItem );
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ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
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int islandIdx = zoneLayer->SubpolyIndex();
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if( zone->IsFilled() )
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{
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const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
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const SHAPE_LINE_CHAIN& padHull = pad->GetEffectivePolygon()->Outline( 0 );
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for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
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{
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// If the entire island is inside the pad's flashing then the pad
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// won't actually connect to anything else, so only return true if
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// part of the island is *outside* the pad's flashing.
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if( !padHull.PointInside( pt ) )
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return true;
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}
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}
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continue;
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}
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else if( aItem->Type() == PCB_VIA_T && zoneLayer )
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{
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const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem );
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ZONE* zone = static_cast<ZONE*>( zoneLayer->Parent() );
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int islandIdx = zoneLayer->SubpolyIndex();
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if( zone->IsFilled() )
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{
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const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
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SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth() / 2 );
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for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
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{
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// If the entire island is inside the via's flashing then the via
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// won't actually connect to anything else, so only return true if
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// part of the island is *outside* the via's flashing.
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if( !viaHull.SHAPE::Collide( pt ) )
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return true;
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}
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}
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continue;
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}
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return true;
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}
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}
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}
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return false;
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}
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unsigned int CONNECTIVITY_DATA::GetUnconnectedCount( bool aVisibleOnly ) const
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{
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unsigned int unconnected = 0;
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for( RN_NET* net : m_nets )
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{
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if( !net )
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continue;
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for( const CN_EDGE& edge : net->GetEdges() )
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{
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if( edge.IsVisible() || !aVisibleOnly )
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++unconnected;
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}
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}
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return unconnected;
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}
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void CONNECTIVITY_DATA::Clear()
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{
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for( RN_NET* net : m_nets )
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delete net;
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m_nets.clear();
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}
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const std::vector<BOARD_CONNECTED_ITEM*>
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CONNECTIVITY_DATA::GetConnectedItems( const BOARD_CONNECTED_ITEM *aItem,
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const std::initializer_list<KICAD_T>& aTypes,
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bool aIgnoreNetcodes ) const
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{
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std::vector<BOARD_CONNECTED_ITEM*> rv;
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CN_CONNECTIVITY_ALGO::CLUSTER_SEARCH_MODE searchMode;
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if( aIgnoreNetcodes )
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searchMode = CN_CONNECTIVITY_ALGO::CSM_PROPAGATE;
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else
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searchMode = CN_CONNECTIVITY_ALGO::CSM_CONNECTIVITY_CHECK;
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const auto clusters = m_connAlgo->SearchClusters( searchMode, aTypes,
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aIgnoreNetcodes ? -1 : aItem->GetNetCode() );
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for( const std::shared_ptr<CN_CLUSTER>& cl : clusters )
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{
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if( cl->Contains( aItem ) )
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{
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for( const CN_ITEM* item : *cl )
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{
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if( item->Valid() )
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rv.push_back( item->Parent() );
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}
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}
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}
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return rv;
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}
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const std::vector<BOARD_CONNECTED_ITEM*>
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CONNECTIVITY_DATA::GetNetItems( int aNetCode, const std::initializer_list<KICAD_T>& aTypes ) const
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{
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std::vector<BOARD_CONNECTED_ITEM*> items;
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items.reserve( 32 );
|
|
|
|
std::bitset<MAX_STRUCT_TYPE_ID> type_bits;
|
|
|
|
for( KICAD_T scanType : aTypes )
|
|
{
|
|
wxASSERT( scanType < MAX_STRUCT_TYPE_ID );
|
|
type_bits.set( scanType );
|
|
}
|
|
|
|
m_connAlgo->ForEachItem(
|
|
[&]( CN_ITEM& aItem )
|
|
{
|
|
if( aItem.Valid() && ( aItem.Net() == aNetCode ) && type_bits[aItem.Parent()->Type()] )
|
|
items.push_back( aItem.Parent() );
|
|
} );
|
|
|
|
std::sort( items.begin(), items.end() );
|
|
items.erase( std::unique( items.begin(), items.end() ), items.end() );
|
|
return items;
|
|
}
|
|
|
|
|
|
const std::vector<PCB_TRACK*>
|
|
CONNECTIVITY_DATA::GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const
|
|
{
|
|
CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
|
|
|
|
std::set<PCB_TRACK*> tracks;
|
|
std::vector<PCB_TRACK*> rv;
|
|
|
|
for( CN_ITEM* citem : entry.GetItems() )
|
|
{
|
|
for( CN_ITEM* connected : citem->ConnectedItems() )
|
|
{
|
|
if( connected->Valid() &&
|
|
( connected->Parent()->Type() == PCB_TRACE_T ||
|
|
connected->Parent()->Type() == PCB_VIA_T ||
|
|
connected->Parent()->Type() == PCB_ARC_T ) )
|
|
{
|
|
tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
|
|
}
|
|
}
|
|
}
|
|
|
|
std::copy( tracks.begin(), tracks.end(), std::back_inserter( rv ) );
|
|
return rv;
|
|
}
|
|
|
|
|
|
void CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem,
|
|
std::set<PAD*>* pads ) const
|
|
{
|
|
for( CN_ITEM* citem : m_connAlgo->ItemEntry( aItem ).GetItems() )
|
|
{
|
|
for( CN_ITEM* connected : citem->ConnectedItems() )
|
|
{
|
|
if( connected->Valid() && connected->Parent()->Type() == PCB_PAD_T )
|
|
pads->insert( static_cast<PAD*> ( connected->Parent() ) );
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
const std::vector<PAD*> CONNECTIVITY_DATA::GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem )
|
|
const
|
|
{
|
|
std::set<PAD*> pads;
|
|
std::vector<PAD*> rv;
|
|
|
|
GetConnectedPads( aItem, &pads );
|
|
|
|
std::copy( pads.begin(), pads.end(), std::back_inserter( rv ) );
|
|
return rv;
|
|
}
|
|
|
|
|
|
unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
|
|
{
|
|
int sum = 0;
|
|
|
|
if( aNet < 0 ) // Node count for all nets
|
|
{
|
|
for( const RN_NET* net : m_nets )
|
|
sum += net->GetNodeCount();
|
|
}
|
|
else if( aNet < (int) m_nets.size() )
|
|
{
|
|
sum = m_nets[aNet]->GetNodeCount();
|
|
}
|
|
|
|
return sum;
|
|
}
|
|
|
|
|
|
unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
|
|
{
|
|
int n = 0;
|
|
|
|
for( CN_ITEM* pad : m_connAlgo->ItemList() )
|
|
{
|
|
if( !pad->Valid() || pad->Parent()->Type() != PCB_PAD_T)
|
|
continue;
|
|
|
|
PAD* dpad = static_cast<PAD*>( pad->Parent() );
|
|
|
|
if( aNet < 0 || aNet == dpad->GetNetCode() )
|
|
n++;
|
|
}
|
|
|
|
return n;
|
|
}
|
|
|
|
|
|
void CONNECTIVITY_DATA::RunOnUnconnectedEdges( std::function<bool( CN_EDGE& )> aFunc )
|
|
{
|
|
for( RN_NET* rnNet : m_nets )
|
|
{
|
|
if( rnNet )
|
|
{
|
|
for( CN_EDGE& edge : rnNet->GetEdges() )
|
|
{
|
|
if( !aFunc( edge ) )
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static int getMinDist( BOARD_CONNECTED_ITEM* aItem, const VECTOR2I& aPoint )
|
|
{
|
|
switch( aItem->Type() )
|
|
{
|
|
case PCB_TRACE_T:
|
|
case PCB_ARC_T:
|
|
{
|
|
PCB_TRACK* track = static_cast<PCB_TRACK*>( aItem );
|
|
|
|
return std::min( GetLineLength( track->GetStart(), aPoint ),
|
|
GetLineLength( track->GetEnd(), aPoint ) );
|
|
}
|
|
|
|
default:
|
|
return GetLineLength( aItem->GetPosition(), aPoint );
|
|
}
|
|
}
|
|
|
|
|
|
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, VECTOR2I* aPos )
|
|
{
|
|
std::list<CN_ITEM*> items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();
|
|
|
|
// Not in the connectivity system. This is a bug!
|
|
if( items.empty() )
|
|
{
|
|
wxFAIL_MSG( wxT( "track not in connectivity system" ) );
|
|
return false;
|
|
}
|
|
|
|
CN_ITEM* citem = items.front();
|
|
|
|
if( !citem->Valid() )
|
|
return false;
|
|
|
|
if( aTrack->Type() == PCB_TRACE_T || aTrack->Type() == PCB_ARC_T )
|
|
{
|
|
// Test if a segment is connected on each end.
|
|
//
|
|
// NB: be wary of short segments which can be connected to the *same* other item on
|
|
// each end. If that's their only connection then they're still dangling.
|
|
|
|
PCB_LAYER_ID layer = aTrack->GetLayer();
|
|
int accuracy = KiROUND( aTrack->GetWidth() / 2 );
|
|
int start_count = 0;
|
|
int end_count = 0;
|
|
|
|
for( CN_ITEM* connected : citem->ConnectedItems() )
|
|
{
|
|
BOARD_CONNECTED_ITEM* item = connected->Parent();
|
|
ZONE* zone = dynamic_cast<ZONE*>( item );
|
|
DRC_RTREE* rtree = nullptr;
|
|
bool hitStart = false;
|
|
bool hitEnd = false;
|
|
|
|
if( item->GetFlags() & IS_DELETED )
|
|
continue;
|
|
|
|
if( zone )
|
|
rtree = zone->GetBoard()->m_CopperZoneRTreeCache[ zone ].get();
|
|
|
|
if( rtree )
|
|
{
|
|
SHAPE_CIRCLE start( aTrack->GetStart(), accuracy );
|
|
SHAPE_CIRCLE end( aTrack->GetEnd(), accuracy );
|
|
|
|
hitStart = rtree->QueryColliding( start.BBox(), &start, layer );
|
|
hitEnd = rtree->QueryColliding( end.BBox(), &end, layer );
|
|
}
|
|
else
|
|
{
|
|
std::shared_ptr<SHAPE> shape = item->GetEffectiveShape( layer );
|
|
|
|
hitStart = shape->Collide( aTrack->GetStart(), accuracy );
|
|
hitEnd = shape->Collide( aTrack->GetEnd(), accuracy );
|
|
}
|
|
|
|
if( hitStart && hitEnd )
|
|
{
|
|
if( getMinDist( item, aTrack->GetStart() ) < getMinDist( item, aTrack->GetEnd() ) )
|
|
start_count++;
|
|
else
|
|
end_count++;
|
|
}
|
|
else if( hitStart )
|
|
{
|
|
start_count++;
|
|
}
|
|
else if( hitEnd )
|
|
{
|
|
end_count++;
|
|
}
|
|
|
|
if( start_count > 0 && end_count > 0 )
|
|
return false;
|
|
}
|
|
|
|
if( aPos )
|
|
*aPos = (start_count == 0 ) ? aTrack->GetStart() : aTrack->GetEnd();
|
|
|
|
return true;
|
|
}
|
|
else if( aTrack->Type() == PCB_VIA_T )
|
|
{
|
|
// Test if a via is only connected on one layer
|
|
|
|
const std::vector<CN_ITEM*>& connected = citem->ConnectedItems();
|
|
|
|
if( connected.empty() )
|
|
{
|
|
if( aPos )
|
|
*aPos = aTrack->GetPosition();
|
|
|
|
return true;
|
|
}
|
|
|
|
// Here, we check if the via is connected only to items on a single layer
|
|
int first_layer = UNDEFINED_LAYER;
|
|
|
|
for( CN_ITEM* item : connected )
|
|
{
|
|
if( item->Parent()->GetFlags() & IS_DELETED )
|
|
continue;
|
|
|
|
if( first_layer == UNDEFINED_LAYER )
|
|
first_layer = item->Layer();
|
|
else if( item->Layer() != first_layer )
|
|
return false;
|
|
}
|
|
|
|
if( aPos )
|
|
*aPos = aTrack->GetPosition();
|
|
|
|
return true;
|
|
}
|
|
else
|
|
{
|
|
wxFAIL_MSG( wxT( "CONNECTIVITY_DATA::TestTrackEndpointDangling: unknown track type" ) );
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
const std::vector<BOARD_CONNECTED_ITEM*>
|
|
CONNECTIVITY_DATA::GetConnectedItemsAtAnchor( const BOARD_CONNECTED_ITEM* aItem,
|
|
const VECTOR2I& aAnchor,
|
|
const std::initializer_list<KICAD_T>& aTypes,
|
|
const int& aMaxError ) const
|
|
{
|
|
CN_CONNECTIVITY_ALGO::ITEM_MAP_ENTRY& entry = m_connAlgo->ItemEntry( aItem );
|
|
std::vector<BOARD_CONNECTED_ITEM*> rv;
|
|
SEG::ecoord maxError_sq = (SEG::ecoord) aMaxError * aMaxError;
|
|
|
|
for( CN_ITEM* cnItem : entry.GetItems() )
|
|
{
|
|
for( CN_ITEM* connected : cnItem->ConnectedItems() )
|
|
{
|
|
for( const std::shared_ptr<CN_ANCHOR>& anchor : connected->Anchors() )
|
|
{
|
|
if( ( anchor->Pos() - aAnchor ).SquaredEuclideanNorm() <= maxError_sq )
|
|
{
|
|
for( KICAD_T type : aTypes )
|
|
{
|
|
if( connected->Valid() && connected->Parent()->Type() == type )
|
|
{
|
|
rv.push_back( connected->Parent() );
|
|
break;
|
|
}
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return rv;
|
|
}
|
|
|
|
|
|
RN_NET* CONNECTIVITY_DATA::GetRatsnestForNet( int aNet )
|
|
{
|
|
if ( aNet < 0 || aNet >= (int) m_nets.size() )
|
|
{
|
|
return nullptr;
|
|
}
|
|
|
|
return m_nets[ aNet ];
|
|
}
|
|
|
|
|
|
void CONNECTIVITY_DATA::MarkItemNetAsDirty( BOARD_ITEM *aItem )
|
|
{
|
|
if ( aItem->Type() == PCB_FOOTPRINT_T)
|
|
{
|
|
for( PAD* pad : static_cast<FOOTPRINT*>( aItem )->Pads() )
|
|
m_connAlgo->MarkNetAsDirty( pad->GetNetCode() );
|
|
}
|
|
if (aItem->IsConnected() )
|
|
{
|
|
m_connAlgo->MarkNetAsDirty( static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() );
|
|
}
|
|
}
|
|
|
|
|
|
void CONNECTIVITY_DATA::SetProgressReporter( PROGRESS_REPORTER* aReporter )
|
|
{
|
|
m_progressReporter = aReporter;
|
|
m_connAlgo->SetProgressReporter( m_progressReporter );
|
|
}
|
|
|
|
|
|
const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForItems( std::vector<BOARD_ITEM*> aItems )
|
|
{
|
|
std::set<int> nets;
|
|
std::vector<CN_EDGE> edges;
|
|
std::set<BOARD_CONNECTED_ITEM*> item_set;
|
|
|
|
for( BOARD_ITEM* item : aItems )
|
|
{
|
|
if( item->Type() == PCB_FOOTPRINT_T )
|
|
{
|
|
FOOTPRINT* footprint = static_cast<FOOTPRINT*>( item );
|
|
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
nets.insert( pad->GetNetCode() );
|
|
item_set.insert( pad );
|
|
}
|
|
}
|
|
else if( auto conn_item = dyn_cast<BOARD_CONNECTED_ITEM*>( item ) )
|
|
{
|
|
item_set.insert( conn_item );
|
|
nets.insert( conn_item->GetNetCode() );
|
|
}
|
|
}
|
|
|
|
for( int netcode : nets )
|
|
{
|
|
RN_NET* net = GetRatsnestForNet( netcode );
|
|
|
|
for( const CN_EDGE& edge : net->GetEdges() )
|
|
{
|
|
std::shared_ptr<CN_ANCHOR> srcNode = edge.GetSourceNode();
|
|
std::shared_ptr<CN_ANCHOR> dstNode = edge.GetTargetNode();
|
|
|
|
BOARD_CONNECTED_ITEM* srcParent = srcNode->Parent();
|
|
BOARD_CONNECTED_ITEM* dstParent = dstNode->Parent();
|
|
|
|
bool srcFound = ( item_set.find( srcParent ) != item_set.end() );
|
|
bool dstFound = ( item_set.find( dstParent ) != item_set.end() );
|
|
|
|
if ( srcFound && dstFound )
|
|
edges.push_back( edge );
|
|
}
|
|
}
|
|
|
|
return edges;
|
|
}
|
|
|
|
|
|
const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForPad( const PAD* aPad )
|
|
{
|
|
std::vector<CN_EDGE> edges;
|
|
RN_NET* net = GetRatsnestForNet( aPad->GetNetCode() );
|
|
|
|
for( const CN_EDGE& edge : net->GetEdges() )
|
|
{
|
|
if( edge.GetSourceNode()->Parent() == aPad || edge.GetTargetNode()->Parent() == aPad )
|
|
edges.push_back( edge );
|
|
}
|
|
|
|
return edges;
|
|
}
|
|
|
|
|
|
const std::vector<CN_EDGE> CONNECTIVITY_DATA::GetRatsnestForComponent( FOOTPRINT* aComponent, bool aSkipInternalConnections )
|
|
{
|
|
std::set<int> nets;
|
|
std::set<const PAD*> pads;
|
|
std::vector<CN_EDGE> edges;
|
|
|
|
for( PAD* pad : aComponent->Pads() )
|
|
{
|
|
nets.insert( pad->GetNetCode() );
|
|
pads.insert( pad );
|
|
}
|
|
|
|
for( const auto& netcode : nets )
|
|
{
|
|
RN_NET* net = GetRatsnestForNet( netcode );
|
|
|
|
for( const CN_EDGE& edge : net->GetEdges() )
|
|
{
|
|
auto srcNode = edge.GetSourceNode();
|
|
auto dstNode = edge.GetTargetNode();
|
|
|
|
const PAD* srcParent = static_cast<const PAD*>( srcNode->Parent() );
|
|
const PAD* dstParent = static_cast<const PAD*>( dstNode->Parent() );
|
|
|
|
bool srcFound = ( pads.find(srcParent) != pads.end() );
|
|
bool dstFound = ( pads.find(dstParent) != pads.end() );
|
|
|
|
if ( srcFound && dstFound && !aSkipInternalConnections )
|
|
{
|
|
edges.push_back( edge );
|
|
}
|
|
else if ( srcFound || dstFound )
|
|
{
|
|
edges.push_back( edge );
|
|
}
|
|
}
|
|
}
|
|
|
|
return edges;
|
|
}
|
|
|
|
|