309 lines
10 KiB
C++
309 lines
10 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2009 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr
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* Copyright (C) 1992-2020 KiCad Developers, see AUTHORS.txt for contributors.
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* Copyright (C) 2018 CERN
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* Author: Maciej Suminski <maciej.suminski@cern.ch>
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* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "pcbnew_printout.h"
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#include <board.h>
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#include <math/util.h> // for KiROUND
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#include <pcb_painter.h>
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#include <pcbnew_settings.h>
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#include <view/view.h>
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#include <pcbplot.h>
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PCBNEW_PRINTOUT_SETTINGS::PCBNEW_PRINTOUT_SETTINGS( const PAGE_INFO& aPageInfo )
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: BOARD_PRINTOUT_SETTINGS( aPageInfo )
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{
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m_drillMarks = SMALL_DRILL_SHAPE;
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m_pagination = ALL_LAYERS;
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m_noEdgeLayer = false;
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m_asItemCheckboxes = false;
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}
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void PCBNEW_PRINTOUT_SETTINGS::Load( APP_SETTINGS_BASE* aConfig )
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{
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BOARD_PRINTOUT_SETTINGS::Load( aConfig );
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if( auto cfg = dynamic_cast<PCBNEW_SETTINGS*>( aConfig ) )
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{
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m_drillMarks = static_cast<DRILL_MARK_SHAPE_T>( cfg->m_Plot.pads_drill_mode );
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m_pagination = static_cast<PAGINATION_T>( cfg->m_Plot.all_layers_on_one_page );
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m_Mirror = cfg->m_Plot.mirror;
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}
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}
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void PCBNEW_PRINTOUT_SETTINGS::Save( APP_SETTINGS_BASE* aConfig )
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{
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BOARD_PRINTOUT_SETTINGS::Save( aConfig );
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if( auto cfg = dynamic_cast<PCBNEW_SETTINGS*>( aConfig ) )
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{
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cfg->m_Plot.pads_drill_mode = m_drillMarks;
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cfg->m_Plot.all_layers_on_one_page = m_pagination;
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cfg->m_Plot.mirror = m_Mirror;
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}
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}
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PCBNEW_PRINTOUT::PCBNEW_PRINTOUT( BOARD* aBoard, const PCBNEW_PRINTOUT_SETTINGS& aParams,
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const KIGFX::VIEW* aView, const wxString& aTitle ) :
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BOARD_PRINTOUT( aParams, aView, aTitle ), m_pcbnewSettings( aParams )
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{
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m_board = aBoard;
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}
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bool PCBNEW_PRINTOUT::OnPrintPage( int aPage )
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{
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// Store the layerset, as it is going to be modified below and the original settings are
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// needed.
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LSET lset = m_settings.m_LayerSet;
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int pageCount = lset.count();
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wxString layerName;
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PCB_LAYER_ID extractLayer;
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// compute layer mask from page number if we want one page per layer
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if( m_pcbnewSettings.m_pagination == PCBNEW_PRINTOUT_SETTINGS::LAYER_PER_PAGE )
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{
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// This sequence is TBD, call a different sequencer if needed, such as Seq().
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// Could not find documentation on page order.
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LSEQ seq = lset.UIOrder();
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// aPage starts at 1, not 0
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if( unsigned( aPage - 1 ) < seq.size() )
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m_settings.m_LayerSet = LSET( seq[ aPage - 1] );
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}
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if( !m_settings.m_LayerSet.any() )
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return false;
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extractLayer = m_settings.m_LayerSet.ExtractLayer();
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if( extractLayer == UNDEFINED_LAYER )
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layerName = _( "Multiple Layers" );
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else
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layerName = LSET::Name( extractLayer );
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// In Pcbnew we can want the layer EDGE always printed
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if( !m_pcbnewSettings.m_noEdgeLayer )
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m_settings.m_LayerSet.set( Edge_Cuts );
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DrawPage( layerName, aPage, pageCount );
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// Restore the original layer set, so the next page can be printed
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m_settings.m_LayerSet = lset;
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return true;
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}
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int PCBNEW_PRINTOUT::milsToIU( double aMils ) const
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{
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return KiROUND( IU_PER_MILS * aMils );
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}
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void PCBNEW_PRINTOUT::setupViewLayers( KIGFX::VIEW& aView, const LSET& aLayerSet )
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{
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BOARD_PRINTOUT::setupViewLayers( aView, aLayerSet );
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for( LSEQ layerSeq = m_settings.m_LayerSet.Seq(); layerSeq; ++layerSeq )
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{
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aView.SetLayerVisible( PCBNEW_LAYER_ID_START + *layerSeq, true );
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// Enable the corresponding zone layer
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if( IsCopperLayer( *layerSeq ) )
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aView.SetLayerVisible( LAYER_ZONE_START + *layerSeq, true );
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}
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if( m_pcbnewSettings.m_asItemCheckboxes )
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{
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auto setVisibility =
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[&]( GAL_LAYER_ID aLayer )
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{
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if( m_board->IsElementVisible( aLayer ) )
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aView.SetLayerVisible( aLayer );
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};
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setVisibility( LAYER_MOD_FR );
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setVisibility( LAYER_MOD_BK );
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setVisibility( LAYER_MOD_VALUES );
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setVisibility( LAYER_MOD_REFERENCES );
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setVisibility( LAYER_MOD_TEXT_FR );
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setVisibility( LAYER_MOD_TEXT_BK );
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setVisibility( LAYER_MOD_TEXT_INVISIBLE );
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setVisibility( LAYER_PAD_FR );
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setVisibility( LAYER_PAD_BK );
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setVisibility( LAYER_PADS_TH );
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setVisibility( LAYER_TRACKS );
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setVisibility( LAYER_VIAS );
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setVisibility( LAYER_NO_CONNECTS );
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setVisibility( LAYER_DRC_WARNING );
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setVisibility( LAYER_DRC_ERROR );
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setVisibility( LAYER_DRC_EXCLUSION );
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setVisibility( LAYER_ANCHOR );
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setVisibility( LAYER_WORKSHEET );
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setVisibility( LAYER_GRID );
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// Keep certain items always enabled and just rely on either the finer or coarser
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// visibility controls
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const int alwaysEnabled[] =
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{
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LAYER_ZONES, LAYER_PADS, LAYER_VIA_MICROVIA, LAYER_VIA_BBLIND,
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LAYER_VIA_THROUGH
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};
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for( int item : alwaysEnabled )
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aView.SetLayerVisible( item, true );
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}
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else
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{
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// Enable pad layers corresponding to the selected copper layers
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if( aLayerSet.test( F_Cu ) )
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aView.SetLayerVisible( LAYER_PAD_FR, true );
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if( aLayerSet.test( B_Cu ) )
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aView.SetLayerVisible( LAYER_PAD_BK, true );
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if( ( aLayerSet & LSET::AllCuMask() ).any() ) // Items visible on any copper layer
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{
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// Enable items on copper layers, but do not draw holes
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for( GAL_LAYER_ID item : { LAYER_PADS_TH, LAYER_VIA_THROUGH } )
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{
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aView.SetLayerVisible( item, true );
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}
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}
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// Keep certain items always enabled/disabled and just rely on the layer visibility
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const int alwaysEnabled[] =
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{
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LAYER_MOD_TEXT_FR, LAYER_MOD_TEXT_BK, LAYER_MOD_FR, LAYER_MOD_BK,
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LAYER_MOD_VALUES, LAYER_MOD_REFERENCES, LAYER_TRACKS, LAYER_ZONES, LAYER_PADS,
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LAYER_VIAS, LAYER_VIA_MICROVIA, LAYER_VIA_BBLIND
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};
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for( int item : alwaysEnabled )
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aView.SetLayerVisible( item, true );
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}
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if( m_pcbnewSettings.m_drillMarks != PCBNEW_PRINTOUT_SETTINGS::NO_DRILL_SHAPE )
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{
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// Enable hole layers to draw drill marks
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for( GAL_LAYER_ID holeLayer : { LAYER_PADS_PLATEDHOLES, LAYER_NON_PLATEDHOLES,
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LAYER_VIAS_HOLES } )
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{
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aView.SetLayerVisible( holeLayer, true );
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aView.SetTopLayer( holeLayer, true );
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}
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}
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}
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void PCBNEW_PRINTOUT::setupPainter( KIGFX::PAINTER& aPainter )
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{
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BOARD_PRINTOUT::setupPainter( aPainter );
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KIGFX::PCB_PRINT_PAINTER& painter = dynamic_cast<KIGFX::PCB_PRINT_PAINTER&>( aPainter );
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switch( m_pcbnewSettings.m_drillMarks )
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{
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case PCBNEW_PRINTOUT_SETTINGS::NO_DRILL_SHAPE:
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painter.SetDrillMarks( false, 0 );
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break;
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case PCBNEW_PRINTOUT_SETTINGS::SMALL_DRILL_SHAPE:
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painter.SetDrillMarks( false, Millimeter2iu( 0.3 ) );
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painter.GetSettings()->SetLayerColor( LAYER_PADS_PLATEDHOLES, COLOR4D::BLACK );
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painter.GetSettings()->SetLayerColor( LAYER_NON_PLATEDHOLES, COLOR4D::BLACK );
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painter.GetSettings()->SetLayerColor( LAYER_VIAS_HOLES, COLOR4D::BLACK );
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break;
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case PCBNEW_PRINTOUT_SETTINGS::FULL_DRILL_SHAPE:
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painter.SetDrillMarks( true );
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painter.GetSettings()->SetLayerColor( LAYER_PADS_PLATEDHOLES, COLOR4D::BLACK );
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painter.GetSettings()->SetLayerColor( LAYER_NON_PLATEDHOLES, COLOR4D::BLACK );
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painter.GetSettings()->SetLayerColor( LAYER_VIAS_HOLES, COLOR4D::BLACK );
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break;
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}
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painter.GetSettings()->SetDrawIndividualViaLayers(
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m_pcbnewSettings.m_pagination == PCBNEW_PRINTOUT_SETTINGS::LAYER_PER_PAGE );
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}
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void PCBNEW_PRINTOUT::setupGal( KIGFX::GAL* aGal )
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{
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BOARD_PRINTOUT::setupGal( aGal );
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aGal->SetWorldUnitLength( 1e-9 /* 1 nm */ / 0.0254 /* 1 inch in meters */ );
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}
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EDA_RECT PCBNEW_PRINTOUT::getBoundingBox()
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{
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return m_board->ComputeBoundingBox();
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}
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std::unique_ptr<KIGFX::PAINTER> PCBNEW_PRINTOUT::getPainter( KIGFX::GAL* aGal )
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{
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return std::make_unique<KIGFX::PCB_PRINT_PAINTER>( aGal );
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}
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KIGFX::PCB_PRINT_PAINTER::PCB_PRINT_PAINTER( GAL* aGal ) :
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PCB_PAINTER( aGal ),
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m_drillMarkReal( false ),
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m_drillMarkSize( 0 )
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{
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m_pcbSettings.EnableZoneOutlines( false );
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}
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int KIGFX::PCB_PRINT_PAINTER::getDrillShape( const PAD* aPad ) const
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{
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return m_drillMarkReal ? KIGFX::PCB_PAINTER::getDrillShape( aPad ) : PAD_DRILL_SHAPE_CIRCLE;
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}
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VECTOR2D KIGFX::PCB_PRINT_PAINTER::getDrillSize( const PAD* aPad ) const
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{
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// TODO should it depend on the pad size?
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return m_drillMarkReal ? KIGFX::PCB_PAINTER::getDrillSize( aPad ) :
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VECTOR2D( m_drillMarkSize, m_drillMarkSize );
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}
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int KIGFX::PCB_PRINT_PAINTER::getDrillSize( const VIA* aVia ) const
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{
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// TODO should it depend on the via size?
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return m_drillMarkReal ? KIGFX::PCB_PAINTER::getDrillSize( aVia ) : m_drillMarkSize;
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}
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