334 lines
14 KiB
C++
334 lines
14 KiB
C++
/**************************************************************/
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/* pcbstruct.h : definition des structures de donnees type PCB */
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/**************************************************************/
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#ifndef PCBSTRUCT_H
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#define PCBSTRUCT_H
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#include "base_struct.h"
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#include "class_base_screen.h"
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#include "board_item_struct.h"
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// Definitions relatives aux libariries
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#define ENTETE_LIBRAIRIE "PCBNEW-LibModule-V1"
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#define ENTETE_LIBDOC "PCBNEW-LibDoc----V1"
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#define L_ENTETE_LIB 18
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#define EXT_DOC wxT( "mdc" )
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/* Bits indicateurs du membre .Status, pour pistes, modules... */
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#define FLAG1 (1 << 13) /* flag libre pour calculs locaux */
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#define FLAG0 (1 << 12) /* flag libre pour calculs locaux */
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#define BEGIN_ONPAD (1 << 11) /* flag indiquant un debut de segment sur pad */
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#define END_ONPAD (1 << 10) /* flag indiquant une fin de segment sur pad */
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#define BUSY (1 << 9) /* flag indiquant que la structure a deja
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* ete examinee, dans certaines routines */
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#define DELETED (1 << 8) /* Bit flag de Status pour structures effacee
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* et mises en chaine "DELETED" */
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#define NO_TRACE (1 << 7) /* l'element ne doit pas etre affiche */
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#define SURBRILL (1 << 5) /* element en surbrillance */
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#define DRAG (1 << 4) /* segment en mode drag */
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#define EDIT (1 << 3) /* element en cours d'edition */
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#define SEGM_FIXE (1 << 2) /* segment FIXE ( pas d'effacement global ) */
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#define SEGM_AR (1 << 1) /* segment Auto_Route */
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#define CHAIN (1 << 0) /* segment marque */
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/* Layer identification (layer number) */
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#define FIRST_COPPER_LAYER 0
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#define COPPER_LAYER_N 0
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#define LAYER_N_2 1 /* Numero layer 2 */
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#define LAYER_N_3 2 /* Numero layer 3 */
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#define LAYER_N_4 3 /* Numero layer 4 */
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#define LAYER_N_5 4 /* Numero layer 5 */
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#define LAYER_N_6 5 /* Numero layer 6 */
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#define LAYER_N_7 6 /* Numero layer 7 */
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#define LAYER_N_8 7 /* Numero layer 8 */
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#define LAYER_N_9 8 /* Numero layer 9 */
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#define LAYER_N_10 9 /* Numero layer 10 */
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#define LAYER_N_11 10 /* Numero layer 11 */
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#define LAYER_N_12 11 /* Numero layer 12 */
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#define LAYER_N_13 12 /* Numero layer 13 */
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#define LAYER_N_14 13 /* Numero layer 14 */
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#define LAYER_N_15 14 /* Numero layer 15 */
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#define LAYER_CMP_N 15
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#define CMP_N 15
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#define LAST_COPPER_LAYER 15
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#define NB_COPPER_LAYERS (LAST_COPPER_LAYER + 1)
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#define FIRST_NO_COPPER_LAYER 16
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#define ADHESIVE_N_CU 16
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#define ADHESIVE_N_CMP 17
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#define SOLDERPASTE_N_CU 18
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#define SOLDERPASTE_N_CMP 19
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#define SILKSCREEN_N_CU 20
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#define SILKSCREEN_N_CMP 21
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#define SOLDERMASK_N_CU 22
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#define SOLDERMASK_N_CMP 23
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#define DRAW_N 24
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#define COMMENT_N 25
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#define ECO1_N 26
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#define ECO2_N 27
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#define EDGE_N 28
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#define LAST_NO_COPPER_LAYER 28
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#define NB_LAYERS (LAST_NO_COPPER_LAYER + 1)
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#define LAYER_COUNT 32
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/*************************************/
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/* constantes de gestion des couches */
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/*************************************/
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#define CUIVRE_LAYER (1 << COPPER_LAYER_N) ///< bit mask for copper layer
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#define LAYER_2 (1 << LAYER_N_2) ///< bit mask for layer 2
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#define LAYER_3 (1 << LAYER_N_3) ///< bit mask for layer 3
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#define LAYER_4 (1 << LAYER_N_4) ///< bit mask for layer 4
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#define LAYER_5 (1 << LAYER_N_5) ///< bit mask for layer 5
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#define LAYER_6 (1 << LAYER_N_6) ///< bit mask for layer 6
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#define LAYER_7 (1 << LAYER_N_7) ///< bit mask for layer 7
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#define LAYER_8 (1 << LAYER_N_8) ///< bit mask for layer 8
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#define LAYER_9 (1 << LAYER_N_9) ///< bit mask for layer 9
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#define LAYER_10 (1 << LAYER_N_10) ///< bit mask for layer 10
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#define LAYER_11 (1 << LAYER_N_11) ///< bit mask for layer 11
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#define LAYER_12 (1 << LAYER_N_12) ///< bit mask for layer 12
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#define LAYER_13 (1 << LAYER_N_13) ///< bit mask for layer 13
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#define LAYER_14 (1 << LAYER_N_14) ///< bit mask for layer 14
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#define LAYER_15 (1 << LAYER_N_15) ///< bit mask for layer 15
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#define CMP_LAYER (1 << LAYER_CMP_N) ///< bit mask for component layer
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#define ADHESIVE_LAYER_CU (1 << ADHESIVE_N_CU)
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#define ADHESIVE_LAYER_CMP (1 << ADHESIVE_N_CMP)
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#define SOLDERPASTE_LAYER_CU (1 << SOLDERPASTE_N_CU)
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#define SOLDERPASTE_LAYER_CMP (1 << SOLDERPASTE_N_CMP)
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#define SILKSCREEN_LAYER_CU (1 << SILKSCREEN_N_CU)
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#define SILKSCREEN_LAYER_CMP (1 << SILKSCREEN_N_CMP)
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#define SOLDERMASK_LAYER_CU (1 << SOLDERMASK_N_CU)
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#define SOLDERMASK_LAYER_CMP (1 << SOLDERMASK_N_CMP)
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#define DRAW_LAYER (1 << DRAW_N)
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#define COMMENT_LAYER (1 << COMMENT_N)
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#define ECO1_LAYER (1 << ECO1_N)
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#define ECO2_LAYER (1 << ECO2_N)
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#define EDGE_LAYER (1 << EDGE_N)
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#define FIRST_NON_COPPER_LAYER ADHESIVE_N_CU
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#define LAST_NON_COPPER_LAYER EDGE_N
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// extra bits 0xE0000000
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/* masques generaux : */
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#define ALL_LAYERS 0x1FFFFFFF
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#define ALL_NO_CU_LAYERS 0x1FFF0000
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#define ALL_CU_LAYERS 0x0000FFFF
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#define INTERNAL_LAYERS 0x00007FFE /* Bits layers internes */
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#define EXTERNAL_LAYERS 0x00008001
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/* Forward declaration */
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class NETINFO_ITEM;
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class MARKER_PCB;
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class RATSNEST_ITEM;
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/* main window classes : */
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#include "wxBasePcbFrame.h"
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/* Class to handle a board */
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#include "class_board.h"
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enum ELEMENTS_NUMBERS
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{
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VIAS_VISIBLE = 0,
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VIA_NOT_DEFINED_VISIBLE = VIAS_VISIBLE,
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VIA_MICROVIA_VISIBLE,
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VIA_BLIND_BURIED_VISIBLE,
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VIA_THROUGH_VISIBLE,
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MODULE_TEXT_CMP_VISIBLE,
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MODULE_TEXT_CU_VISIBLE,
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MODULE_TEXT_NOV_VISIBLE,
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ANCHOR_VISIBLE,
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PAD_CU_VISIBLE,
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PAD_CMP_VISIBLE
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};
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// Class for handle current printed board design settings
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class EDA_BoardDesignSettings
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{
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public:
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int m_CopperLayerCount; // Number of copper layers for this design
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int m_ViaDrill; // via drill (for the entire board)
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int m_ViaDrillCustomValue; // via drill for vias which must have a defined drill value
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int m_MicroViaDrill; // micro via drill (for the entire board)
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int m_CurrentViaSize; // Current via size
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int m_CurrentMicroViaSize; // Current micro via size
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bool m_MicroViasAllowed; // true to allow micro vias
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int m_CurrentViaType; // via type (VIA_BLIND_BURIED, VIA_TROUGHT VIA_MICROVIA)
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int m_CurrentTrackWidth; // current track width
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bool m_UseConnectedTrackWidth; // if true, when creating a new track starting on an existing track, use this track width
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int m_DrawSegmentWidth; // current graphic line width (not EDGE layer)
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int m_EdgeSegmentWidth; // current graphic line width (EDGE layer only)
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int m_PcbTextWidth; // current Pcb (not module) Text width
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wxSize m_PcbTextSize; // current Pcb (not module) Text size
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int m_TrackClearance; // track to track and track to pads clearance
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int m_TrackMinWidth; // track min value for width ((min copper size value
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int m_ViasMinSize; // vias (not micro vias) min diameter
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int m_MicroViasMinSize; // micro vias (not vias) min diameter
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int m_MaskMargin; // Solder mask margin
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int m_LayerThickness; // Layer Thickness for 3D viewer
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// Color options for screen display of the Printed Board:
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//@@IMB: Not used int m_PcbGridColor; // Grid color
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int m_EnabledLayers; // IMB: Paving the road
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int m_VisibleLayers; // IMB: Bit-mask for layer visibility
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int m_VisibleElements; // IMB: Bit-mask for elements visibility
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int m_LayerColor[32]; // Layer colors (tracks and graphic items)
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int m_ViaColor[4]; // Via color (depending on is type)
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//@@IMB: Not used int m_ModuleTextCMPColor; // Text module color for modules on the COMPONENT layer
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//@@IMB: Not used int m_ModuleTextCUColor; // Text module color for modules on the COPPER layer
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//@@IMB: Not used int m_ModuleTextNOVColor; // Text module color for "invisible" texts (must be BLACK if really not displayed)
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//@@IMB: Not used int m_AnchorColor; // Anchor color for modules and texts
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//@@IMB: Not used int m_PadCUColor; // Pad color for the COPPER side of the pad
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//@@IMB: Not used int m_PadCMPColor; // Pad color for the COMPONENT side of the pad
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// Pad color for the pads of both sides is m_PadCUColor OR m_PadCMPColor (in terms of colors)
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int m_RatsnestColor; // Ratsnest color
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public:
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EDA_BoardDesignSettings();
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/**
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* Function GetVisibleLayers
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* returns a bit-map of all the layers that are visible.
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* @return int - the visible layers in bit-mapped form.
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*/
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int GetVisibleLayers() const;
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void SetVisibleLayers( int Mask );
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/**
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* Function IsLayerVisible
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* @param LayerNumber The number of the layer to be tested.
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* @return bool - true if the layer is visible.
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*/
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inline bool IsLayerVisible( int LayerNumber ) const
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{
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if( LayerNumber < 0 || LayerNumber >= 32 ) //@@IMB: Altough Pcbnew uses only 29, Gerbview uses all 32 layers
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return false;
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return (bool)( m_VisibleLayers & 1 << LayerNumber );
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}
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void SetLayerVisibility( int LayerNumber, bool State );
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/**
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* Function IsElementVisible
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* @param ElementNumber The number of the element to be tested.
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* @return bool - true if the elememt is visible.
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*/
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inline bool IsElementVisible( int ElementNumber ) const
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{
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if( ElementNumber < 0 || ElementNumber > PAD_CMP_VISIBLE )
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return false;
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return (bool)( m_VisibleElements & 1 << ElementNumber );
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}
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void SetElementVisibility( int ElementNumber, bool State );
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};
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// Values for m_DisplayViaMode member:
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enum DisplayViaMode {
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VIA_HOLE_NOT_SHOW = 0,
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VIA_SPECIAL_HOLE_SHOW,
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ALL_VIA_HOLE_SHOW,
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OPT_VIA_HOLE_END
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};
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/* Handle info to display a board */
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#include "class_pcb_screen.h"
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/**********************************/
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/* Module (Footprint) description */
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/**********************************/
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#include "class_pad.h" // class for pads
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#include "class_edge_mod.h" // Class for footprint graphic elements
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#include "class_text_mod.h" // Class for footprint fields
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#include "class_module.h" // Class for the footprint
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#include "class_netinfo.h" // Class for nets
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/***********************************/
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/* Description des elements du PCB */
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/***********************************/
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#include "class_drawsegment.h"
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#include "class_pcb_text.h"
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#include "class_cotation.h"
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#include "class_mire.h"
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#include "class_track.h"
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#include "class_marker_pcb.h"
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#include "class_zone.h"
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/* Values for DISPLAY_OPTIONS.ShowTrackClearanceMode parameter option
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* This parameter controls how to show tracks and vias clerance area
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*/
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enum ShowTrackClearanceModeList {
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DO_NOT_SHOW_CLEARANCE = 0, // Do not show clearance areas
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SHOW_CLEARANCE_NEW_TRACKS, // Show clearance areas only for new track during track creation
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SHOW_CLEARANCE_NEW_TRACKS_AND_VIA_AREAS, /* Show clrearance areas only for new track during track creation,
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* and shows a via clearnce area at end of current new segment (guide to place a nev via
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*/
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SHOW_CLEARANCE_ALWAYS // Show Always clearance areas for track and vias
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};
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class DISPLAY_OPTIONS
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{
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public:
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bool DisplayPadFill;
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bool DisplayViaFill;
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bool DisplayPadNum;
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bool DisplayPadNoConn;
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bool DisplayPadIsol;
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int DisplayModEdge;
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int DisplayModText;
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bool DisplayPcbTrackFill; /* FALSE = sketch , TRUE = filled */
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int ShowTrackClearanceMode; /* = 0 , 1 or 2
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* 0 = do not show clearance
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* 1 = show track clearance
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* 2 = show clearance + via area
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* (useful to know what clearance area is neede if we want to put a via on terminal track point)
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*/
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int m_DisplayViaMode; /* 0 do not show via hole,
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* 1 show via hole for non default value
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* 2 show all via hole */
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bool DisplayPolarCood;
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int DisplayZonesMode;
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int DisplayNetNamesMode; /* 0 do not show netnames,
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* 1 show netnames on pads
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* 2 show netnames on tracks
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* 3 show netnames on tracks and pads
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*/
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bool Show_Modules_Cmp;
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bool Show_Modules_Cu;
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int DisplayDrawItems;
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bool ContrastModeDisplay;
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public:
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DISPLAY_OPTIONS();
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};
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#endif /* PCBSTRUCT_H */
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