233 lines
8.3 KiB
C++
233 lines
8.3 KiB
C++
/**
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* @file class_board_design_settings.cpp
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* BOARD_DESIGN_SETTINGS class functions.
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*/
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#include <fctsys.h>
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#include <common.h>
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#include <layers_id_colors_and_visibility.h>
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#include <pcbnew.h>
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#include <class_board_design_settings.h>
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#include <class_track.h>
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#include <convert_from_iu.h>
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// Board thickness, mainly for 3D view:
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#define DEFAULT_BOARD_THICKNESS_MM 1.6
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// Default values for some board items
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#define DEFAULT_TEXT_PCB_SIZE Millimeter2iu( 1.5 )
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#define DEFAULT_TEXT_PCB_THICKNESS Millimeter2iu( 0.3 )
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#define DEFAULT_PCB_EDGE_THICKNESS Millimeter2iu( 0.15 )
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#define DEFAULT_GRAPHIC_THICKNESS Millimeter2iu( 0.2 )
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#define DEFAULT_TEXT_MODULE_SIZE Millimeter2iu( 1.5 )
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#define DEFAULT_GR_MODULE_THICKNESS Millimeter2iu( 0.15 )
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#define DEFAULT_SOLDERMASK_CLEARANCE Millimeter2iu( 0.2 )
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#define DEFAULT_SOLDERMASK_MIN_WIDTH Millimeter2iu( 0.0 )
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BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS() :
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m_Pad_Master( 0 )
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{
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m_EnabledLayers = ALL_LAYERS; // All layers enabled at first.
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// SetCopperLayerCount() will adjust this.
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SetVisibleLayers( FULL_LAYERS );
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// set all but hidden text as visible.
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m_VisibleElements = ~( 1 << MOD_TEXT_INVISIBLE );
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SetCopperLayerCount( 2 ); // Default design is a double sided board
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// via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA).
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m_CurrentViaType = VIA_THROUGH;
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// if true, when creating a new track starting on an existing track, use this track width
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m_UseConnectedTrackWidth = false;
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m_MicroViasAllowed = false; // true to allow micro vias
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m_DrawSegmentWidth = DEFAULT_GRAPHIC_THICKNESS; // current graphic line width (not EDGE layer)
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m_EdgeSegmentWidth = DEFAULT_PCB_EDGE_THICKNESS; // current graphic line width (EDGE layer only)
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m_PcbTextWidth = DEFAULT_TEXT_PCB_THICKNESS; // current Pcb (not module) Text width
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m_PcbTextSize = wxSize( DEFAULT_TEXT_PCB_SIZE,
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DEFAULT_TEXT_PCB_SIZE ); // current Pcb (not module) Text size
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m_TrackMinWidth = DMils2iu( 100 ); // track min value for width ((min copper size value
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m_ViasMinSize = DMils2iu( 350 ); // vias (not micro vias) min diameter
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m_ViasMinDrill = DMils2iu( 200 ); // vias (not micro vias) min drill diameter
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m_MicroViasMinSize = DMils2iu( 200 ); // micro vias (not vias) min diameter
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m_MicroViasMinDrill = DMils2iu( 50 ); // micro vias (not vias) min drill diameter
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// Global mask margins:
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m_SolderMaskMargin = DEFAULT_SOLDERMASK_CLEARANCE; // Solder mask margin
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m_SolderMaskMinWidth = DEFAULT_SOLDERMASK_MIN_WIDTH; // Solder mask min width
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m_SolderPasteMargin = 0; // Solder paste margin absolute value
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m_SolderPasteMarginRatio = 0.0; // Solder pask margin ratio value of pad size
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// The final margin is the sum of these 2 values
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// Usually < 0 because the mask is smaller than pad
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m_ModuleTextSize = wxSize( DEFAULT_TEXT_MODULE_SIZE,
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DEFAULT_TEXT_MODULE_SIZE );
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m_ModuleTextWidth = DEFAULT_GR_MODULE_THICKNESS;
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m_ModuleSegmentWidth = DEFAULT_GR_MODULE_THICKNESS;
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// Layer thickness for 3D viewer
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m_boardThickness = Millimeter2iu( DEFAULT_BOARD_THICKNESS_MM );
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}
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// Add parameters to save in project config.
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// values are saved in mm
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void BOARD_DESIGN_SETTINGS::AppendConfigs( PARAM_CFG_ARRAY* aResult )
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{
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m_Pad_Master.AppendConfigs( aResult );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeV" ),
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&m_PcbTextSize.y,
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DEFAULT_TEXT_PCB_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeH" ),
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&m_PcbTextSize.x,
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DEFAULT_TEXT_PCB_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextThickness" ),
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&m_PcbTextWidth,
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DEFAULT_TEXT_PCB_THICKNESS,
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeV" ),
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&m_ModuleTextSize.y,
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DEFAULT_TEXT_MODULE_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeH" ),
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&m_ModuleTextSize.x,
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DEFAULT_TEXT_MODULE_SIZE, TEXTS_MIN_SIZE, TEXTS_MAX_SIZE,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeThickness" ),
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&m_ModuleTextWidth,
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DEFAULT_GR_MODULE_THICKNESS, 1, TEXTS_MAX_WIDTH,
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskClearance" ),
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&m_SolderMaskMargin,
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DEFAULT_SOLDERMASK_CLEARANCE, 0, Millimeter2iu( 1.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskMinWidth" ),
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&m_SolderMaskMinWidth,
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DEFAULT_SOLDERMASK_MIN_WIDTH, 0, Millimeter2iu( 0.5 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "DrawSegmentWidth" ),
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&m_DrawSegmentWidth,
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DEFAULT_GRAPHIC_THICKNESS,
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "BoardOutlineThickness" ),
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&m_EdgeSegmentWidth,
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DEFAULT_PCB_EDGE_THICKNESS,
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleOutlineThickness" ),
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&m_ModuleSegmentWidth,
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DEFAULT_GR_MODULE_THICKNESS,
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Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
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NULL, MM_PER_IU ) );
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}
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// see pcbstruct.h
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int BOARD_DESIGN_SETTINGS::GetVisibleLayers() const
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{
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return m_VisibleLayers;
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}
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void BOARD_DESIGN_SETTINGS::SetVisibleAlls()
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{
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SetVisibleLayers( FULL_LAYERS );
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m_VisibleElements = -1;
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}
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void BOARD_DESIGN_SETTINGS::SetVisibleLayers( int aMask )
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{
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// Although Pcbnew uses only 29, GerbView uses all 32 layers
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m_VisibleLayers = aMask & m_EnabledLayers & FULL_LAYERS;
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}
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void BOARD_DESIGN_SETTINGS::SetLayerVisibility( int aLayerIndex, bool aNewState )
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{
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// Altough Pcbnew uses only 29, GerbView uses all 32 layers
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if( aLayerIndex < 0 || aLayerIndex >= 32 )
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return;
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if( aNewState && IsLayerEnabled( aLayerIndex ) )
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m_VisibleLayers |= 1 << aLayerIndex;
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else
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m_VisibleLayers &= ~( 1 << aLayerIndex );
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}
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void BOARD_DESIGN_SETTINGS::SetElementVisibility( int aElementCategory, bool aNewState )
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{
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if( aElementCategory < 0 || aElementCategory >= END_PCB_VISIBLE_LIST )
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return;
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if( aNewState )
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m_VisibleElements |= 1 << aElementCategory;
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else
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m_VisibleElements &= ~( 1 << aElementCategory );
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}
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void BOARD_DESIGN_SETTINGS::SetCopperLayerCount( int aNewLayerCount )
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{
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// if( aNewLayerCount < 2 ) aNewLayerCount = 2;
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m_CopperLayerCount = aNewLayerCount;
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// ensure consistency with the m_EnabledLayers member
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m_EnabledLayers &= ~ALL_CU_LAYERS;
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m_EnabledLayers |= LAYER_BACK;
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if( m_CopperLayerCount > 1 )
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m_EnabledLayers |= LAYER_FRONT;
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for( int ii = 1; ii < aNewLayerCount - 1; ii++ )
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m_EnabledLayers |= 1 << ii;
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}
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void BOARD_DESIGN_SETTINGS::SetEnabledLayers( int aMask )
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{
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// Back and front layers are always enabled.
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aMask |= LAYER_BACK | LAYER_FRONT;
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m_EnabledLayers = aMask;
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// A disabled layer cannot be visible
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m_VisibleLayers &= aMask;
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// update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
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m_CopperLayerCount = 0;
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for( int ii = 0; aMask && ii < NB_COPPER_LAYERS; ii++, aMask >>= 1 )
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{
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if( aMask & 1 )
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m_CopperLayerCount++;
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}
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}
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