196 lines
6.6 KiB
C++
196 lines
6.6 KiB
C++
/**********************************************************************/
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/* fonctions membres des classes utilisees dans pcbnew (voir pcbstruct.h */
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/* sauf routines relatives aux pistes (voir class_track.cpp) */
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/**********************************************************************/
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#include "fctsys.h"
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#include "wxstruct.h"
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#include "gr_basic.h"
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#include "common.h"
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#include "pcbnew.h"
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#ifdef CVPCB
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#include "cvpcb.h"
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#endif
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#include "trigo.h"
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/**************************************************/
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/* Class SCREEN: classe de gestion d'un affichage */
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/***************************************************/
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/* Constructeur de SCREEN */
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PCB_SCREEN::PCB_SCREEN( int idscreen ) : BASE_SCREEN( TYPESCREEN )
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{
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// a zero terminated list
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static const int zoom_list[] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 0 };
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m_Type = idscreen;
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SetGridList( g_GridList );
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SetZoomList( zoom_list );
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m_Grid = wxSize( 500, 500 ); /* pas de la grille en 1/10000 "*/
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Init();
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}
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/***************************/
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PCB_SCREEN::~PCB_SCREEN()
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/***************************/
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{
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}
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/*************************/
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void PCB_SCREEN::Init()
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/*************************/
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{
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InitDatas();
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m_Active_Layer = COPPER_LAYER_N; /* ref couche active 0.. 31 */
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m_Route_Layer_TOP = CMP_N; /* ref couches par defaut pour vias (Cu.. Cmp) */
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m_Route_Layer_BOTTOM = COPPER_LAYER_N;
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m_Zoom = 128; /* valeur */
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}
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/* Return true if a microvia can be put on board
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* A microvia ia a small via restricted to 2 near neighbour layers
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* because its is hole is made by laser which can penetrate only one layer
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* It is mainly used to connect BGA to the first inner layer
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* And it is allowed from an external layer to the first inner layer
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*/
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bool PCB_SCREEN::IsMicroViaAcceptable( void )
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{
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int copperlayercnt = g_DesignSettings.m_CopperLayerCount;
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if( !g_DesignSettings.m_MicroViasAllowed )
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return false; // Obvious..
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if( copperlayercnt < 4 )
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return false; // Only on multilayer boards..
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if( (m_Active_Layer == COPPER_LAYER_N)
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|| (m_Active_Layer == LAYER_CMP_N)
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|| (m_Active_Layer == g_DesignSettings.m_CopperLayerCount - 2)
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|| (m_Active_Layer == LAYER_N_2) )
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return true;
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return false;
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}
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/*************************/
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/* class DISPLAY_OPTIONS */
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/*************************/
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/*
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* Handle display options like enable/disable some optional drawings:
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*/
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DISPLAY_OPTIONS::DISPLAY_OPTIONS()
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{
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DisplayPadFill = TRUE;
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DisplayPadNum = TRUE;
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DisplayPadNoConn = TRUE;
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DisplayPadIsol = TRUE;
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DisplayModEdge = TRUE;
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DisplayModText = TRUE;
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DisplayPcbTrackFill = TRUE; /* FALSE = sketch , TRUE = rempli */
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DisplayTrackIsol = FALSE;
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m_DisplayViaMode = VIA_HOLE_NOT_SHOW;
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DisplayPolarCood = TRUE;
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DisplayZones = TRUE;
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Show_Modules_Cmp = TRUE;
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Show_Modules_Cu = TRUE;
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DisplayDrawItems = TRUE;
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ContrastModeDisplay = FALSE;
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}
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/*****************************************************/
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EDA_BoardDesignSettings::EDA_BoardDesignSettings()
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/*****************************************************/
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// Default values for designing boards
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{
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int ii;
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static const int default_layer_color[32] = {
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GREEN, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, RED,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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MAGENTA, CYAN,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY
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};
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m_CopperLayerCount = 2; // Default design is a double sided board
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m_ViaDrill = 250; // defualt via drill (for the entire board)
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m_ViaDrillCustomValue = 250; // via drill for vias which must have a defined drill value
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m_CurrentViaSize = 450; // Current via size
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m_CurrentViaType = VIA_THROUGH; // via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA)
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m_CurrentTrackWidth = 170; // current track width
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m_UseConnectedTrackWidth = false; // if true, when creating a new track starting on an existing track, use this track width
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m_MicroViaDrill = 50; // micro via drill (for the entire board)
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m_CurrentMicroViaSize = 150; // Current micro via size
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m_MicroViasAllowed = false; // true to allow micro vias
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for( ii = 0; ii < HISTORY_NUMBER; ii++ )
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{
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m_TrackWidthHistory[ii] = 0; // Last HISTORY_NUMBER used track widths
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m_ViaSizeHistory[ii] = 0; // Last HISTORY_NUMBER used via sizes
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}
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m_DrawSegmentWidth = 100; // current graphic line width (not EDGE layer)
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m_EdgeSegmentWidth = 100; // current graphic line width (EDGE layer only)
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m_PcbTextWidth = 100; // current Pcb (not module) Text width
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m_PcbTextSize = wxSize( 500, 500 ); // current Pcb (not module) Text size
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m_TrackClearence = 100; // track to track and track to pads clearance
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m_MaskMargin = 150; // Solder mask margin
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/* Color options for screen display of the Printed Board: */
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m_PcbGridColor = DARKGRAY; // Grid color
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for( ii = 0; ii < 32; ii++ )
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m_LayerColor[ii] = default_layer_color[ii];
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// Layer colors (tracks and graphic items)
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m_ViaColor[VIA_NOT_DEFINED] = DARKGRAY;
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m_ViaColor[VIA_MICROVIA] = CYAN;
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m_ViaColor[VIA_BLIND_BURIED] = BROWN;
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m_ViaColor[VIA_THROUGH] = WHITE;
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m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer
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m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer
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m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed)
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m_AnchorColor = BLUE; // Anchor color for modules and texts
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m_PadCUColor = GREEN; // Pad color for the COMPONENT side of the pad
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m_PadCMPColor = RED; // Pad color for the COPPER side of the pad
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m_RatsnestColor = WHITE; // Ratsnest color
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}
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// see pcbstruct.h
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int EDA_BoardDesignSettings::GetVisibleLayers() const
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{
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int layerMask = 0;
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for( int i = 0, mask = 1; i< 32; ++i, mask <<= 1 )
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{
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if( !(m_LayerColor[i] & ITEM_NOT_SHOW) )
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layerMask |= mask;
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}
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return layerMask;
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}
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