392 lines
4.1 KiB
Plaintext
392 lines
4.1 KiB
Plaintext
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# Copyright (C) 2007-2011 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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# These are keywords for the Specctra DSN (s-expression) lexer and parser.
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absolute
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added
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add_group
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add_pins
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allow_antenna
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allow_redundant_wiring
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amp
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ancestor
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antipad
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aperture_type
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array
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attach
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attr
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average_pair_length
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back
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base_design
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bbv_ctr2ctr
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bend_keepout
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bond
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both
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bottom
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bottom_layer_sel
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boundary
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brickpat
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bundle
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bus
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bypass
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capacitance_resolution
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capacitor
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case_sensitive
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cct1
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cct1a
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center_center
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checking_trim_by_pin
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circ
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circle
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circuit
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class
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class_class
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classes
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clear
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clearance
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cluster
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cm
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color
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colors
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comment
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comp
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comp_edge_center
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comp_order
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component
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composite
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conductance_resolution
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conductor
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conflict
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connect
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constant
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contact
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control
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corner
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corners
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cost
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created_time
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cross
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crosstalk_model
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current_resolution
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deleted
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deleted_keepout
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delta
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diagonal
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direction
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directory
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discrete
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effective_via_length
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elongate_keepout
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exclude
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expose
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extra_image_directory
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family
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family_family
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family_family_spacing
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fanout
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farad
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file
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fit
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fix
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flip_style
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floor_plan
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footprint
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forbidden
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force_to_terminal_point
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forgotten
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free
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fromto
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front
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front_only
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gap
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gate
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gates
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generated_by_freeroute
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global
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grid
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group
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group_set
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guide
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hard
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height
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high
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history
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horizontal
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host_cad
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host_version
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image
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image_conductor
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image_image
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image_image_spacing
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image_outline_clearance
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image_set
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image_type
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inch
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include
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include_pins_in_crosstalk
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inductance_resolution
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insert
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instcnfg
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inter_layer_clearance
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jumper
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junction_type
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keepout
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kg
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kohm
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large
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large_large
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layer
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layer_depth
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layer_noise_weight
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layer_pair
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layer_rule
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length
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length_amplitude
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length_factor
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length_gap
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library
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library_out
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limit
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limit_bends
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limit_crossing
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limit_vias
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limit_way
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linear
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linear_interpolation
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load
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lock_type
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logical_part
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logical_part_mapping
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low
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match_fromto_delay
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match_fromto_length
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match_group_delay
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match_group_length
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match_net_delay
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match_net_length
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max_delay
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max_len
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max_length
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max_noise
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max_restricted_layer_length
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max_stagger
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max_stub
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max_total_delay
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max_total_length
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max_total_vias
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medium
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mhenry
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mho
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microvia
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mid_driven
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mil
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min_gap
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mirror
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mirror_first
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mixed
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mm
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negative_diagonal
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net
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net_number
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net_out
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net_pin_changes
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nets
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network
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network_out
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no
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noexpose
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noise_accumulation
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noise_calculation
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normal
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object_type
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off
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off_grid
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offset
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on
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open
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opposite_side
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order
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orthogonal
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outline
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overlap
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pad
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pad_pad
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padstack
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pair
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parallel
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parallel_noise
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parallel_segment
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parser
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part_library
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path
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pcb
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permit_orient
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permit_side
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physical
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physical_part_mapping
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piggyback
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pin
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pin_allow
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pin_cap_via
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pin_via_cap
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pin_width_taper
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pins
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pintype
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place
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place_boundary
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place_control
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place_keepout
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place_rule
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placement
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plan
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plane
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pn
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point
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polyline_path
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polygon
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position
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positive_diagonal
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power
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power_dissipation
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power_fanout
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prefix
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primary
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priority
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property
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protect
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qarc
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quarter
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radius
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ratio
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ratio_tolerance
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rect
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reduced
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region
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region_class
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region_class_class
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region_net
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relative_delay
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relative_group_delay
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relative_group_length
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relative_length
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reorder
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reroute_order_viols
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resistance_resolution
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resistor
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resolution
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restricted_layer_length_factor
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room
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rotate
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rotate_first
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round
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roundoff_rotation
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route
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route_to_fanout_only
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routes
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routes_include
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rule
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same_net_checking
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sample_window
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saturation_length
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sec
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secondary
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self
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sequence_number
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session
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set_color
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set_pattern
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shape
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shield
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shield_gap
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shield_loop
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shield_tie_down_interval
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shield_width
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side
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signal
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site
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small
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smd
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snap
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snap_angle
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soft
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source
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space_in_quoted_tokens
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spacing
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spare
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spiral_via
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square
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stack_via
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stack_via_depth
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standard
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starburst
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status
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structure
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structure_out
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subgate
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subgates
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substituted
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such
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suffix
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super_placement
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supply
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supply_pin
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swapping
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switch_window
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system
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tandem_noise
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tandem_segment
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tandem_shield_overhang
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terminal
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terminator
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term_only
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test
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test_points
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testpoint
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threshold
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time_length_factor
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time_resolution
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tjunction
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tolerance
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top
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topology
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total
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track_id
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turret
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type
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um
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unassigned
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unconnects
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unit
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up
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use_array
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use_layer
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use_net
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use_via
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value
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vertical
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via
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via_array_template
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via_at_smd
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via_keepout
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via_number
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via_rotate_first
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via_site
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via_size
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virtual_pin
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volt
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voltage_resolution
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was_is
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way
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weight
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width
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window
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wire
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wire_keepout
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wires
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wires_include
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wiring
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write_resolution
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x # test cmake script with indent and comment
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xy
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y
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