437 lines
15 KiB
C++
437 lines
15 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2023 KiCad Developers.
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*
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* This program is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <board.h>
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#include <board_design_settings.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <drc/drc_length_report.h>
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#include <connectivity/connectivity_data.h>
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#include <connectivity/from_to_cache.h>
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/*
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Single-ended matched length + skew + via count test.
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Errors generated:
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- DRCE_LENGTH_OUT_OF_RANGE
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- DRCE_SKEW_OUT_OF_RANGE
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- DRCE_TOO_MANY_VIAS
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Todo: arc support
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*/
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class DRC_TEST_PROVIDER_MATCHED_LENGTH : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_MATCHED_LENGTH () :
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m_board( nullptr )
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{
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}
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virtual ~DRC_TEST_PROVIDER_MATCHED_LENGTH()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "length" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests matched track lengths." );
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}
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private:
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bool runInternal( bool aDelayReportMode = false );
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using CONNECTION = DRC_LENGTH_REPORT::ENTRY;
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void checkLengths( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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void checkSkews( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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void checkViaCounts( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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private:
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BOARD* m_board;
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DRC_LENGTH_REPORT m_report;
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};
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkLengths( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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{
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for( const DRC_LENGTH_REPORT::ENTRY& ent : aMatchedConnections )
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{
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bool minViolation = false;
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bool maxViolation = false;
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int minLen = 0;
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int maxLen = 0;
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if( aConstraint.GetValue().HasMin() && ent.total < aConstraint.GetValue().Min() )
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{
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minViolation = true;
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minLen = aConstraint.GetValue().Min();
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}
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else if( aConstraint.GetValue().HasMax() && ent.total > aConstraint.GetValue().Max() )
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{
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maxViolation = true;
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maxLen = aConstraint.GetValue().Max();
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}
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if( ( minViolation || maxViolation ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_LENGTH_OUT_OF_RANGE );
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wxString msg;
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if( minViolation )
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{
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msg = formatMsg( _( "(%s min length %s; actual %s)" ),
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aConstraint.GetName(),
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minLen,
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ent.total );
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}
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else if( maxViolation )
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{
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msg = formatMsg( _( "(%s max length %s; actual %s)" ),
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aConstraint.GetName(),
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maxLen,
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ent.total );
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}
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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for( auto offendingTrack : ent.items )
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drcItem->AddItem( offendingTrack );
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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}
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}
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}
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkSkews( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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{
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double avgLength = 0;
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for( const DRC_LENGTH_REPORT::ENTRY& ent : aMatchedConnections )
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avgLength += ent.total;
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avgLength /= (double) aMatchedConnections.size();
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for( const auto& ent : aMatchedConnections )
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{
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int skew = KiROUND( ent.total - avgLength );
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bool fail_min = false;
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bool fail_max = false;
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if( aConstraint.GetValue().HasMax() && abs( skew ) > aConstraint.GetValue().Max() )
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fail_max = true;
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else if( aConstraint.GetValue().HasMin() && abs( skew ) < aConstraint.GetValue().Min() )
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fail_min = true;
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if( fail_min || fail_max )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SKEW_OUT_OF_RANGE );
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wxString msg;
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if( fail_min )
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{
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msg.Printf( _( "(%s min skew %s; actual %s; average net length %s; actual %s)" ),
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aConstraint.GetName(),
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MessageTextFromValue( aConstraint.GetValue().Min() ),
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MessageTextFromValue( skew ),
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MessageTextFromValue( avgLength ),
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MessageTextFromValue( ent.total ) );
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}
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else
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{
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msg.Printf( _( "(%s max skew %s; actual %s; average net length %s; actual %s)" ),
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aConstraint.GetName(),
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MessageTextFromValue( aConstraint.GetValue().Max() ),
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MessageTextFromValue( skew ),
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MessageTextFromValue( avgLength ),
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MessageTextFromValue( ent.total ) );
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}
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drcItem->SetErrorMessage( drcItem->GetErrorText() + " " + msg );
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for( BOARD_CONNECTED_ITEM* offendingTrack : ent.items )
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drcItem->SetItems( offendingTrack );
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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}
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}
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}
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkViaCounts( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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{
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for( const auto& ent : aMatchedConnections )
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{
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if( aConstraint.GetValue().HasMax() && ent.viaCount > aConstraint.GetValue().Max() )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TOO_MANY_VIAS );
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wxString msg = wxString::Format( _( "(%s max count %d; actual %d)" ),
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aConstraint.GetName(),
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aConstraint.GetValue().Max(),
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ent.viaCount );
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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for( auto offendingTrack : ent.items )
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drcItem->SetItems( offendingTrack );
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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}
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}
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}
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bool DRC_TEST_PROVIDER_MATCHED_LENGTH::Run()
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{
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return runInternal( false );
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}
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bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
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{
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m_board = m_drcEngine->GetBoard();
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m_report.Clear();
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if( !aDelayReportMode )
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{
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if( !reportPhase( _( "Gathering length-constrained connections..." ) ) )
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return false;
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}
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std::map<DRC_RULE*, std::set<BOARD_CONNECTED_ITEM*> > itemSets;
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std::shared_ptr<FROM_TO_CACHE> ftCache = m_board->GetConnectivity()->GetFromToCache();
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ftCache->Rebuild( m_board );
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const size_t progressDelta = 100;
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size_t count = 0;
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size_t ii = 0;
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forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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count++;
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return true;
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} );
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forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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if( !reportProgress( ii++, count, progressDelta ) )
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return false;
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const DRC_CONSTRAINT_T constraintsToCheck[] = {
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LENGTH_CONSTRAINT,
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SKEW_CONSTRAINT,
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VIA_COUNT_CONSTRAINT,
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};
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for( int i = 0; i < 3; i++ )
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{
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auto constraint = m_drcEngine->EvalRules( constraintsToCheck[i], item, nullptr,
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item->GetLayer() );
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if( constraint.IsNull() )
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continue;
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auto citem = static_cast<BOARD_CONNECTED_ITEM*>( item );
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itemSets[ constraint.GetParentRule() ].insert( citem );
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}
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return true;
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} );
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std::map< DRC_RULE*, std::vector<CONNECTION> > matches;
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for( const std::pair< DRC_RULE* const, std::set<BOARD_CONNECTED_ITEM*> >& it : itemSets )
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{
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std::map<int, std::set<BOARD_CONNECTED_ITEM*> > netMap;
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for( BOARD_CONNECTED_ITEM* citem : it.second )
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netMap[ citem->GetNetCode() ].insert( citem );
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for( const std::pair< const int, std::set<BOARD_CONNECTED_ITEM*> >& nitem : netMap )
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{
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CONNECTION ent;
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ent.items = nitem.second;
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ent.netcode = nitem.first;
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ent.netname = m_board->GetNetInfo().GetNetItem( ent.netcode )->GetNetname();
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ent.viaCount = 0;
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ent.totalRoute = 0;
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ent.totalVia = 0;
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ent.totalPadToDie = 0;
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ent.fromItem = nullptr;
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ent.toItem = nullptr;
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for( BOARD_CONNECTED_ITEM* citem : nitem.second )
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{
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if( citem->Type() == PCB_VIA_T )
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{
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const BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
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const BOARD_STACKUP& stackup = bds.GetStackupDescriptor();
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ent.viaCount++;
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if( bds.m_UseHeightForLengthCalcs )
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{
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const PCB_VIA* v = static_cast<PCB_VIA*>( citem );
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PCB_LAYER_ID topmost;
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PCB_LAYER_ID bottommost;
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v->GetOutermostConnectedLayers( &topmost, &bottommost );
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if( topmost != UNDEFINED_LAYER && topmost != bottommost )
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ent.totalVia += stackup.GetLayerDistance( topmost, bottommost );
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}
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}
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else if( citem->Type() == PCB_TRACE_T )
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{
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ent.totalRoute += static_cast<PCB_TRACK*>( citem )->GetLength();
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}
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else if ( citem->Type() == PCB_ARC_T )
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{
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ent.totalRoute += static_cast<PCB_ARC*>( citem )->GetLength();
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}
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else if( citem->Type() == PCB_PAD_T )
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{
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ent.totalPadToDie += static_cast<PAD*>( citem )->GetPadToDieLength();
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}
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}
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ent.total = ent.totalRoute + ent.totalVia + ent.totalPadToDie;
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ent.matchingRule = it.first;
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// fixme: doesn't seem to work ;-)
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auto ftPath = ftCache->QueryFromToPath( ent.items );
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if( ftPath )
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{
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ent.from = ftPath->fromName;
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ent.to = ftPath->toName;
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}
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else
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{
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ent.from = ent.to = _( "<unconstrained>" );
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}
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m_report.Add( ent );
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matches[ it.first ].push_back(ent);
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}
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}
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if( !aDelayReportMode )
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{
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if( !reportPhase( _( "Checking length constraints..." ) ) )
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return false;
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ii = 0;
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count = matches.size();
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for( std::pair< DRC_RULE* const, std::vector<CONNECTION> > it : matches )
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{
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DRC_RULE *rule = it.first;
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auto& matchedConnections = it.second;
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if( !reportProgress( ii++, count, progressDelta ) )
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return false;
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std::sort( matchedConnections.begin(), matchedConnections.end(),
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[] ( const CONNECTION&a, const CONNECTION&b ) -> int
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{
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return a.netname < b.netname;
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} );
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reportAux( wxString::Format( wxT( "Length-constrained traces for rule '%s':" ),
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it.first->m_Name ) );
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for( const DRC_LENGTH_REPORT::ENTRY& ent : matchedConnections )
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{
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reportAux(wxString::Format( wxT( " - net: %s, from: %s, to: %s, "
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"%d matching items, "
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"total: %s (tracks: %s, vias: %s, pad-to-die: %s), "
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"vias: %d" ),
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ent.netname,
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ent.from,
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ent.to,
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(int) ent.items.size(),
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MessageTextFromValue( ent.total ),
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MessageTextFromValue( ent.totalRoute ),
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MessageTextFromValue( ent.totalVia ),
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MessageTextFromValue( ent.totalPadToDie ),
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ent.viaCount ) );
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}
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std::optional<DRC_CONSTRAINT> lengthConstraint = rule->FindConstraint( LENGTH_CONSTRAINT );
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if( lengthConstraint && lengthConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
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checkLengths( *lengthConstraint, matchedConnections );
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std::optional<DRC_CONSTRAINT> skewConstraint = rule->FindConstraint( SKEW_CONSTRAINT );
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if( skewConstraint && skewConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
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checkSkews( *skewConstraint, matchedConnections );
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std::optional<DRC_CONSTRAINT> viaCountConstraint = rule->FindConstraint( VIA_COUNT_CONSTRAINT );
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if( viaCountConstraint && viaCountConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
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checkViaCounts( *viaCountConstraint, matchedConnections );
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}
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reportRuleStatistics();
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}
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MATCHED_LENGTH> dummy;
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}
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