1018 lines
37 KiB
C++
1018 lines
37 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <math_for_graphics.h>
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#include <board_design_settings.h>
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#include <footprint.h>
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#include <pcb_shape.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <zone.h>
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#include <geometry/seg.h>
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#include <geometry/shape_poly_set.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_rtree.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <pcb_dimension.h>
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/*
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Copper clearance test. Checks all copper items (pads, vias, tracks, drawings, zones) for their
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electrical clearance.
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Errors generated:
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- DRCE_CLEARANCE
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- DRCE_HOLE_CLEARANCE
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- DRCE_TRACKS_CROSSING
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- DRCE_ZONES_INTERSECT
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- DRCE_SHORTING_ITEMS
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*/
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class DRC_TEST_PROVIDER_COPPER_CLEARANCE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
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{
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public:
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DRC_TEST_PROVIDER_COPPER_CLEARANCE () :
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DRC_TEST_PROVIDER_CLEARANCE_BASE(),
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m_drcEpsilon( 0 )
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{
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}
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virtual ~DRC_TEST_PROVIDER_COPPER_CLEARANCE()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "clearance" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests copper item clearance" );
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}
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private:
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/**
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* Checks for track/via/hole <-> clearance
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* @param track Track to text
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* @param trackShape Primitive track shape
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* @param layer Which layer to test (in case of vias this can be multiple
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* @param other item against which to test the track item
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* @return false if there is a clearance violation reported, true if there is none
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*/
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bool testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer,
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BOARD_ITEM* other );
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void testTrackClearances();
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bool testPadAgainstItem( PAD* pad, SHAPE* padShape, PCB_LAYER_ID layer, BOARD_ITEM* other );
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void testPadClearances();
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void testZonesToZones();
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void testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone, PCB_LAYER_ID aLayer );
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typedef struct checked
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{
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checked()
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: layers(), has_error( false ) {}
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checked( PCB_LAYER_ID aLayer )
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: layers( aLayer ), has_error( false ) {}
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LSET layers;
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bool has_error;
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} layers_checked;
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private:
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int m_drcEpsilon;
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};
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run()
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{
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m_board = m_drcEngine->GetBoard();
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if( m_board->m_DRCMaxClearance <= 0 )
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{
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reportAux( wxT( "No Clearance constraints found. Tests not run." ) );
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return true; // continue with other tests
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}
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m_drcEpsilon = m_board->GetDesignSettings().GetDRCEpsilon();
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking track & via clearances..." ) ) )
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return false; // DRC cancelled
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testTrackClearances();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking hole clearances..." ) ) )
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return false; // DRC cancelled
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testTrackClearances();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking pad clearances..." ) ) )
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return false; // DRC cancelled
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testPadClearances();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS )
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|| !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking pads..." ) ) )
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return false; // DRC cancelled
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testPadClearances();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper zone clearances..." ) ) )
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return false; // DRC cancelled
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testZonesToZones();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_ZONES_INTERSECT ) )
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{
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if( !reportPhase( _( "Checking zones..." ) ) )
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return false; // DRC cancelled
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testZonesToZones();
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}
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reportRuleStatistics();
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return !m_drcEngine->IsCancelled();
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}
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape,
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PCB_LAYER_ID layer,
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BOARD_ITEM* other )
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{
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
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DRC_CONSTRAINT constraint;
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int clearance = -1;
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int actual;
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VECTOR2I pos;
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bool has_error = false;
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std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( layer );
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if( other->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( other );
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if( pad->GetAttribute() == PAD_ATTRIB::NPTH && !pad->FlashLayer( layer ) )
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testClearance = false;
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}
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if( testClearance )
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{
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, track, other, layer );
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clearance = constraint.GetValue().Min();
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}
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
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{
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// Special processing for track:track intersections
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if( track->Type() == PCB_TRACE_T && other->Type() == PCB_TRACE_T )
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{
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SEG trackSeg( track->GetStart(), track->GetEnd() );
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SEG otherSeg( track->GetStart(), track->GetEnd() );
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if( OPT_VECTOR2I intersection = trackSeg.Intersect( otherSeg ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACKS_CROSSING );
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drcItem->SetItems( track, other );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, *intersection, layer );
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return false;
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}
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}
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if( trackShape->Collide( otherShape.get(), clearance - m_drcEpsilon, &actual, &pos ) )
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{
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if( m_drcEngine->IsNetTieExclusion( track->GetNetCode(), layer, pos, other ) )
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{
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// Collision occurred as track was entering a pad marked as a net-tie. We
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// allow these.
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}
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else
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( track, other );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, layer );
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has_error = true;
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if( !m_drcEngine->GetReportAllTrackErrors() )
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return false;
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}
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}
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}
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if( testHoles && ( track->HasHole() || other->HasHole() ) )
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{
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std::array<BOARD_ITEM*, 2> a{ track, other };
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std::array<BOARD_ITEM*, 2> b{ other, track };
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std::array<SHAPE*, 2> a_shape{ trackShape, otherShape.get() };
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for( size_t ii = 0; ii < 2; ++ii )
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{
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std::shared_ptr<SHAPE_SEGMENT> holeShape;
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// We only test a track item here against an item with a hole.
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// If either case is not valid, simply move on
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if( !( dynamic_cast<PCB_TRACK*>( a[ii] ) ) || !b[ii]->HasHole() )
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{
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continue;
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}
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if( b[ii]->Type() == PCB_VIA_T )
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{
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if( b[ii]->GetLayerSet().Contains( layer ) )
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holeShape = b[ii]->GetEffectiveHoleShape();
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}
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else
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{
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holeShape = b[ii]->GetEffectiveHoleShape();
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}
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constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, b[ii], a[ii], layer );
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clearance = constraint.GetValue().Min();
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// Test for hole to item clearance even if clearance is 0, because the item cannot be
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// inside (or intersect) the hole.
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
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{
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if( a_shape[ii]->Collide( holeShape.get(), std::max( 0, clearance - m_drcEpsilon ),
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&actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
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wxString msg = formatMsg( clearance ? _( "(%s clearance %s; actual %s)" )
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: _( "(%s clearance %s; actual < 0)" ),
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constraint.GetName(),
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clearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( a[ii], b[ii] );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, layer );
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return false;
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}
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}
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}
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}
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return !has_error;
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}
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void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone,
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PCB_LAYER_ID aLayer )
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{
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if( !aZone->GetLayerSet().test( aLayer ) )
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return;
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if( aZone->GetNetCode() && aItem->IsConnected() )
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{
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if( aZone->GetNetCode() == static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() )
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return;
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}
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BOX2I itemBBox = aItem->GetBoundingBox();
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BOX2I worstCaseBBox = itemBBox;
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worstCaseBBox.Inflate( m_board->m_DRCMaxClearance );
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if( !worstCaseBBox.Intersects( aZone->GetBoundingBox() ) )
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return;
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
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if( !testClearance && !testHoles )
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return;
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DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ aZone ].get();
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if( !zoneTree )
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return;
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DRC_CONSTRAINT constraint;
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int clearance = -1;
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int actual;
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VECTOR2I pos;
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if( aItem->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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bool flashedPad = pad->FlashLayer( aLayer );
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bool platedHole = pad->HasHole() && pad->GetAttribute() == PAD_ATTRIB::PTH;
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if( !flashedPad && !platedHole )
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testClearance = false;
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}
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if( testClearance )
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{
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
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clearance = constraint.GetValue().Min();
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}
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
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{
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std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer, FLASHING::DEFAULT );
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if( zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
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std::max( 0, clearance - m_drcEpsilon ), &actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( aItem, aZone );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, aLayer );
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}
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}
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if( testHoles && aItem->HasHole() )
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{
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std::shared_ptr<SHAPE_SEGMENT> holeShape;
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if( aItem->Type() == PCB_VIA_T )
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{
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if( aItem->GetLayerSet().Contains( aLayer ) )
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holeShape = aItem->GetEffectiveHoleShape();
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}
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else
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{
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holeShape = aItem->GetEffectiveHoleShape();
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}
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if( holeShape )
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{
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constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
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clearance = constraint.GetValue().Min();
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
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{
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if( zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
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std::max( 0, clearance - m_drcEpsilon ),
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&actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( aItem, aZone );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, aLayer );
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}
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}
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}
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}
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}
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void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
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{
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// This is the number of tests between 2 calls to the progress bar
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const int progressDelta = 100;
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int ii = 0;
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reportAux( wxT( "Testing %d tracks & vias..." ), m_board->Tracks().size() );
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std::map<BOARD_ITEM*, int> freePadsUsageMap;
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std::unordered_map<PTR_PTR_CACHE_KEY, layers_checked> checkedPairs;
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for( PCB_TRACK* track : m_board->Tracks() )
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{
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if( !reportProgress( ii++, m_board->Tracks().size(), progressDelta ) )
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break;
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for( PCB_LAYER_ID layer : LSET( track->GetLayerSet() & LSET::AllCuMask() ).Seq() )
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{
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std::shared_ptr<SHAPE> trackShape = track->GetEffectiveShape( layer );
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m_board->m_CopperItemRTreeCache->QueryColliding( track, layer, layer,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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auto otherCItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( other );
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if( otherCItem && otherCItem->GetNetCode() == track->GetNetCode() )
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return false;
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BOARD_ITEM* a = track;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions
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// (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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auto it = checkedPairs.find( { a, b } );
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if( it != checkedPairs.end() && ( it->second.layers.test( layer )
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|| ( it->second.has_error && !m_drcEngine->GetReportAllTrackErrors() ) ) )
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{
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return false;
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}
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else
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{
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checkedPairs[ { a, b } ].layers.set( layer );
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return true;
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}
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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if( other->Type() == PCB_PAD_T && static_cast<PAD*>( other )->IsFreePad() )
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{
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if( other->GetEffectiveShape( layer )->Collide( trackShape.get() ) )
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{
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auto it = freePadsUsageMap.find( other );
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if( it == freePadsUsageMap.end() )
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{
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freePadsUsageMap[ other ] = track->GetNetCode();
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return false;
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}
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else if( it->second == track->GetNetCode() )
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{
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return false;
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}
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}
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}
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BOARD_ITEM* a = track;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions
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// (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
// If we get an error, mark the pair as having a clearance error already
|
|
// Only continue if we are reporting all track errors
|
|
if( !testTrackAgainstItem( track, trackShape.get(), layer, other ) )
|
|
{
|
|
if( it != checkedPairs.end() )
|
|
it->second.has_error = true;
|
|
|
|
return m_drcEngine->GetReportAllTrackErrors() && !m_drcEngine->IsCancelled();
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
},
|
|
m_board->m_DRCMaxClearance );
|
|
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
testItemAgainstZone( track, zone, layer );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* padShape,
|
|
PCB_LAYER_ID aLayer,
|
|
BOARD_ITEM* other )
|
|
{
|
|
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
|
|
bool testShorting = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
|
|
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
|
|
|
|
// Disable some tests for net-tie objects in a footprint
|
|
if( other->GetParent() == pad->GetParent() )
|
|
{
|
|
FOOTPRINT* fp = static_cast<FOOTPRINT*>( pad->GetParent() );
|
|
std::map<wxString, int> padToNetTieGroupMap = fp->MapPadNumbersToNetTieGroups();
|
|
int padGroupIdx = padToNetTieGroupMap[ pad->GetNumber() ];
|
|
|
|
if( other->Type() == PCB_PAD_T )
|
|
{
|
|
PAD* otherPad = static_cast<PAD*>( other );
|
|
|
|
if( padGroupIdx >= 0 && padGroupIdx == padToNetTieGroupMap[ otherPad->GetNumber() ] )
|
|
testClearance = false;
|
|
|
|
if( pad->SameLogicalPadAs( otherPad ) )
|
|
testHoles = false;
|
|
}
|
|
|
|
if( other->Type() == PCB_FP_SHAPE_T && padGroupIdx >= 0 )
|
|
testClearance = false;
|
|
}
|
|
|
|
PAD* otherPad = nullptr;
|
|
PCB_VIA* otherVia = nullptr;
|
|
|
|
if( other->Type() == PCB_PAD_T )
|
|
otherPad = static_cast<PAD*>( other );
|
|
|
|
if( other->Type() == PCB_VIA_T )
|
|
otherVia = static_cast<PCB_VIA*>( other );
|
|
|
|
if( !IsCopperLayer( aLayer ) )
|
|
testClearance = false;
|
|
|
|
// A NPTH has no cylinder, but it may still have pads on some layers
|
|
if( pad->GetAttribute() == PAD_ATTRIB::NPTH && !pad->FlashLayer( aLayer ) )
|
|
testClearance = false;
|
|
|
|
if( otherPad && otherPad->GetAttribute() == PAD_ATTRIB::NPTH && !otherPad->FlashLayer( aLayer ) )
|
|
testClearance = false;
|
|
|
|
// Track clearances are tested in testTrackClearances()
|
|
if( dynamic_cast<PCB_TRACK*>( other) )
|
|
testClearance = false;
|
|
|
|
int padNet = pad->GetNetCode();
|
|
int otherPadNet = otherPad ? otherPad->GetNetCode() : 0;
|
|
int otherViaNet = otherVia ? otherVia->GetNetCode() : 0;
|
|
|
|
// Pads and vias of the same (defined) net get a waiver on clearance and hole tests
|
|
if( ( otherPadNet && otherPadNet == padNet ) || ( otherViaNet && otherViaNet == padNet ) )
|
|
{
|
|
testClearance = false;
|
|
testHoles = false;
|
|
}
|
|
|
|
if( !( pad->GetDrillSize().x > 0 )
|
|
&& !( otherPad && otherPad->GetDrillSize().x > 0 )
|
|
&& !( otherVia && otherVia->GetDrill() > 0 ) )
|
|
{
|
|
testHoles = false;
|
|
}
|
|
|
|
if( !testClearance && !testShorting && !testHoles )
|
|
return false;
|
|
|
|
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( aLayer );
|
|
DRC_CONSTRAINT constraint;
|
|
int clearance;
|
|
int actual;
|
|
VECTOR2I pos;
|
|
|
|
if( otherPad && pad->SameLogicalPadAs( otherPad ) )
|
|
{
|
|
// If pads are equivalent (ie: from the same footprint with the same pad number)...
|
|
// ... and have nets...
|
|
// then they must be the same net
|
|
if( pad->GetNetCode() && otherPad->GetNetCode()
|
|
&& pad->GetNetCode() != otherPad->GetNetCode()
|
|
&& testShorting )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
|
|
wxString msg;
|
|
|
|
msg.Printf( _( "(nets %s and %s)" ),
|
|
pad->GetNetname(),
|
|
otherPad->GetNetname() );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
drce->SetItems( pad, otherPad );
|
|
|
|
reportViolation( drce, otherPad->GetPosition(), aLayer );
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
}
|
|
|
|
if( testClearance )
|
|
{
|
|
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, pad, other, aLayer );
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
|
|
{
|
|
if( padShape->Collide( otherShape.get(), std::max( 0, clearance - m_drcEpsilon ),
|
|
&actual, &pos ) )
|
|
{
|
|
if( m_drcEngine->IsNetTieExclusion( pad->GetNetCode(), aLayer, pos, other ) )
|
|
{
|
|
// Pads connected to pads of a net-tie footprint are allowed to collide
|
|
// with the net-tie footprint's graphics.
|
|
}
|
|
else
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
drce->SetItems( pad, other );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pos, aLayer );
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if( testHoles )
|
|
{
|
|
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, pad, other, aLayer );
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
|
|
testHoles = false;
|
|
}
|
|
|
|
if( testHoles && otherPad && pad->FlashLayer( aLayer ) && otherPad->HasHole() )
|
|
{
|
|
if( clearance > 0 && padShape->Collide( otherPad->GetEffectiveHoleShape().get(),
|
|
std::max( 0, clearance - m_drcEpsilon ),
|
|
&actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
drce->SetItems( pad, other );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pos, aLayer );
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
}
|
|
|
|
if( testHoles && otherPad && otherPad->FlashLayer( aLayer ) && pad->HasHole() )
|
|
{
|
|
if( clearance > 0 && otherShape->Collide( pad->GetEffectiveHoleShape().get(),
|
|
std::max( 0, clearance - m_drcEpsilon ),
|
|
&actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
drce->SetItems( pad, other );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pos, aLayer );
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
}
|
|
|
|
if( testHoles && otherVia && otherVia->IsOnLayer( aLayer ) )
|
|
{
|
|
if( clearance > 0 && padShape->Collide( otherVia->GetEffectiveHoleShape().get(),
|
|
std::max( 0, clearance - m_drcEpsilon ),
|
|
&actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
drce->SetItems( pad, otherVia );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pos, aLayer );
|
|
}
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
|
|
{
|
|
const int progressDelta = 100;
|
|
size_t count = 0;
|
|
int ii = 0;
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
count += footprint->Pads().size();
|
|
|
|
reportAux( wxT( "Testing %d pads..." ), count );
|
|
|
|
std::unordered_map<PTR_PTR_CACHE_KEY, int> checkedPairs;
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
for( PCB_LAYER_ID layer : pad->GetLayerSet().Seq() )
|
|
{
|
|
std::shared_ptr<SHAPE> padShape = pad->GetEffectiveShape( layer );
|
|
|
|
m_board->m_CopperItemRTreeCache->QueryColliding( pad, layer, layer,
|
|
// Filter:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
BOARD_ITEM* a = pad;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both directions
|
|
// (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
if( checkedPairs.find( { a, b } ) != checkedPairs.end() )
|
|
{
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
checkedPairs[ { a, b } ] = 1;
|
|
return true;
|
|
}
|
|
},
|
|
// Visitor
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
return testPadAgainstItem( pad, padShape.get(), layer, other );
|
|
},
|
|
m_board->m_DRCMaxClearance );
|
|
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
testItemAgainstZone( pad, zone, layer );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
}
|
|
|
|
if( !reportProgress( ii++, count, progressDelta ) )
|
|
return;
|
|
}
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
|
|
{
|
|
const int progressDelta = 50;
|
|
|
|
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
|
|
bool testIntersects = !m_drcEngine->IsErrorLimitExceeded( DRCE_ZONES_INTERSECT );
|
|
|
|
SHAPE_POLY_SET buffer;
|
|
SHAPE_POLY_SET* boardOutline = nullptr;
|
|
DRC_CONSTRAINT constraint;
|
|
int zone2zoneClearance;
|
|
|
|
if( m_board->GetBoardPolygonOutlines( buffer ) )
|
|
boardOutline = &buffer;
|
|
|
|
for( int layer_id = F_Cu; layer_id <= B_Cu; ++layer_id )
|
|
{
|
|
PCB_LAYER_ID layer = static_cast<PCB_LAYER_ID>( layer_id );
|
|
std::vector<SHAPE_POLY_SET> smoothed_polys;
|
|
smoothed_polys.resize( m_board->m_DRCCopperZones.size() );
|
|
|
|
// Skip over layers not used on the current board
|
|
if( !m_board->IsLayerEnabled( layer ) )
|
|
continue;
|
|
|
|
for( size_t ii = 0; ii < m_board->m_DRCCopperZones.size(); ii++ )
|
|
{
|
|
if( m_board->m_DRCCopperZones[ii]->IsOnLayer( layer ) )
|
|
{
|
|
m_board->m_DRCCopperZones[ii]->BuildSmoothedPoly( smoothed_polys[ii], layer,
|
|
boardOutline );
|
|
}
|
|
}
|
|
|
|
// iterate through all areas
|
|
for( size_t ia = 0; ia < m_board->m_DRCCopperZones.size(); ia++ )
|
|
{
|
|
if( !reportProgress( layer_id * m_board->m_DRCCopperZones.size() + ia,
|
|
B_Cu * m_board->m_DRCCopperZones.size(), progressDelta ) )
|
|
{
|
|
return; // DRC cancelled
|
|
}
|
|
|
|
ZONE* zoneA = m_board->m_DRCCopperZones[ia];
|
|
|
|
if( !zoneA->IsOnLayer( layer ) )
|
|
continue;
|
|
|
|
for( size_t ia2 = ia + 1; ia2 < m_board->m_DRCCopperZones.size(); ia2++ )
|
|
{
|
|
ZONE* zoneB = m_board->m_DRCCopperZones[ia2];
|
|
|
|
// test for same layer
|
|
if( !zoneB->IsOnLayer( layer ) )
|
|
continue;
|
|
|
|
// Test for same net
|
|
if( zoneA->GetNetCode() == zoneB->GetNetCode() && zoneA->GetNetCode() >= 0 )
|
|
continue;
|
|
|
|
// test for different priorities
|
|
if( zoneA->GetAssignedPriority() != zoneB->GetAssignedPriority() )
|
|
continue;
|
|
|
|
// rule areas may overlap at will
|
|
if( zoneA->GetIsRuleArea() || zoneB->GetIsRuleArea() )
|
|
continue;
|
|
|
|
// Examine a candidate zone: compare zoneB to zoneA
|
|
|
|
// Get clearance used in zone to zone test.
|
|
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneA, zoneB, layer );
|
|
zone2zoneClearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
|
|
continue;
|
|
|
|
if( testIntersects )
|
|
{
|
|
// test for some corners of zoneA inside zoneB
|
|
for( auto it = smoothed_polys[ia].IterateWithHoles(); it; it++ )
|
|
{
|
|
VECTOR2I currentVertex = *it;
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
if( smoothed_polys[ia2].Contains( currentVertex ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
drce->SetItems( zoneA, zoneB );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pt, layer );
|
|
}
|
|
}
|
|
|
|
// test for some corners of zoneB inside zoneA
|
|
for( auto it = smoothed_polys[ia2].IterateWithHoles(); it; it++ )
|
|
{
|
|
VECTOR2I currentVertex = *it;
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
if( smoothed_polys[ia].Contains( currentVertex ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
drce->SetItems( zoneB, zoneA );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, pt, layer );
|
|
}
|
|
}
|
|
}
|
|
|
|
// Iterate through all the segments of refSmoothedPoly
|
|
std::map<VECTOR2I, int> conflictPoints;
|
|
|
|
for( auto refIt = smoothed_polys[ia].IterateSegmentsWithHoles(); refIt; refIt++ )
|
|
{
|
|
// Build ref segment
|
|
SEG refSegment = *refIt;
|
|
|
|
// Iterate through all the segments in smoothed_polys[ia2]
|
|
for( auto it = smoothed_polys[ia2].IterateSegmentsWithHoles(); it; it++ )
|
|
{
|
|
// Build test segment
|
|
SEG testSegment = *it;
|
|
VECTOR2I pt;
|
|
|
|
int ax1, ay1, ax2, ay2;
|
|
ax1 = refSegment.A.x;
|
|
ay1 = refSegment.A.y;
|
|
ax2 = refSegment.B.x;
|
|
ay2 = refSegment.B.y;
|
|
|
|
int bx1, by1, bx2, by2;
|
|
bx1 = testSegment.A.x;
|
|
by1 = testSegment.A.y;
|
|
bx2 = testSegment.B.x;
|
|
by2 = testSegment.B.y;
|
|
|
|
int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2, 0,
|
|
ax1, ay1, ax2, ay2, 0,
|
|
zone2zoneClearance, &pt.x, &pt.y );
|
|
|
|
if( d < zone2zoneClearance )
|
|
{
|
|
if( conflictPoints.count( pt ) )
|
|
conflictPoints[ pt ] = std::min( conflictPoints[ pt ], d );
|
|
else
|
|
conflictPoints[ pt ] = d;
|
|
}
|
|
}
|
|
}
|
|
|
|
for( const std::pair<const VECTOR2I, int>& conflict : conflictPoints )
|
|
{
|
|
int actual = conflict.second;
|
|
std::shared_ptr<DRC_ITEM> drce;
|
|
|
|
if( actual <= 0 && testIntersects )
|
|
{
|
|
drce = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
}
|
|
else if( testClearance )
|
|
{
|
|
drce = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
zone2zoneClearance,
|
|
std::max( actual, 0 ) );
|
|
|
|
drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
|
|
}
|
|
|
|
if( drce )
|
|
{
|
|
drce->SetItems( zoneA, zoneB );
|
|
drce->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
reportViolation( drce, conflict.first, layer );
|
|
}
|
|
}
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
namespace detail
|
|
{
|
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_COPPER_CLEARANCE> dummy;
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}
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