411 lines
12 KiB
C++
411 lines
12 KiB
C++
// Copyright 2014 The Crashpad Authors. All rights reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_
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#define CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_
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#include <stdint.h>
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#include "snapshot/cpu_architecture.h"
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#include "util/numeric/int128.h"
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namespace crashpad {
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//! \brief A context structure carrying 32-bit x86 CPU state.
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struct CPUContextX86 {
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using X87Register = uint8_t[10];
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struct Fsave {
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uint16_t fcw; // FPU control word
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uint16_t reserved_1;
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uint16_t fsw; // FPU status word
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uint16_t reserved_2;
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uint16_t ftw; // full FPU tag word
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uint16_t reserved_3;
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uint32_t fpu_ip; // FPU instruction pointer offset
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uint16_t fpu_cs; // FPU instruction pointer segment selector
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uint16_t fop; // FPU opcode
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uint32_t fpu_dp; // FPU data pointer offset
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uint16_t fpu_ds; // FPU data pointer segment selector
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uint16_t reserved_4;
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X87Register st[8];
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};
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union X87OrMMXRegister {
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struct {
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X87Register st;
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uint8_t st_reserved[6];
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};
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struct {
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uint8_t mm_value[8];
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uint8_t mm_reserved[8];
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};
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};
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using XMMRegister = uint8_t[16];
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struct Fxsave {
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uint16_t fcw; // FPU control word
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uint16_t fsw; // FPU status word
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uint8_t ftw; // abridged FPU tag word
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uint8_t reserved_1;
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uint16_t fop; // FPU opcode
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uint32_t fpu_ip; // FPU instruction pointer offset
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uint16_t fpu_cs; // FPU instruction pointer segment selector
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uint16_t reserved_2;
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uint32_t fpu_dp; // FPU data pointer offset
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uint16_t fpu_ds; // FPU data pointer segment selector
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uint16_t reserved_3;
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uint32_t mxcsr; // multimedia extensions status and control register
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uint32_t mxcsr_mask; // valid bits in mxcsr
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X87OrMMXRegister st_mm[8];
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XMMRegister xmm[8];
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uint8_t reserved_4[176];
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uint8_t available[48];
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};
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//! \brief Converts an `fxsave` area to an `fsave` area.
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//!
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//! `fsave` state is restricted to the x87 FPU, while `fxsave` state includes
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//! state related to the x87 FPU as well as state specific to SSE.
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//!
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//! As the `fxsave` format is a superset of the `fsave` format, this operation
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//! fully populates the `fsave` area. `fsave` uses the full 16-bit form for
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//! the x87 floating-point tag word, so FxsaveToFsaveTagWord() is used to
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//! derive Fsave::ftw from the abridged 8-bit form used by `fxsave`. Reserved
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//! fields in \a fsave are set to `0`.
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//!
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//! \param[in] fxsave The `fxsave` area to convert.
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//! \param[out] fsave The `fsave` area to populate.
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//!
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//! \sa FsaveToFxsave()
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static void FxsaveToFsave(const Fxsave& fxsave, Fsave* fsave);
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//! \brief Converts an `fsave` area to an `fxsave` area.
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//!
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//! `fsave` state is restricted to the x87 FPU, while `fxsave` state includes
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//! state related to the x87 FPU as well as state specific to SSE.
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//!
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//! As the `fsave` format is a subset of the `fxsave` format, this operation
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//! cannot fully populate the `fxsave` area. Fields in \a fxsave that have no
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//! equivalent in \a fsave are set to `0`, including Fxsave::mxcsr,
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//! Fxsave::mxcsr_mask, Fxsave::xmm, and Fxsave::available.
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//! FsaveToFxsaveTagWord() is used to derive Fxsave::ftw from the full 16-bit
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//! form used by `fsave`. Reserved fields in \a fxsave are set to `0`.
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//!
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//! \param[in] fsave The `fsave` area to convert.
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//! \param[out] fxsave The `fxsave` area to populate.
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//!
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//! \sa FxsaveToFsave()
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static void FsaveToFxsave(const Fsave& fsave, Fxsave* fxsave);
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//! \brief Converts x87 floating-point tag words from `fxsave` (abridged,
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//! 8-bit) to `fsave` (full, 16-bit) form.
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//!
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//! `fxsave` stores the x87 floating-point tag word in abridged 8-bit form,
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//! and `fsave` stores it in full 16-bit form. Some users, notably
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//! CPUContextX86::Fsave::ftw, require the full 16-bit form, where most other
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//! contemporary code uses `fxsave` and thus the abridged 8-bit form found in
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//! CPUContextX86::Fxsave::ftw.
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//!
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//! This function converts an abridged tag word to the full version by using
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//! the abridged tag word and the contents of the registers it describes. See
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//! Intel Software Developer’s Manual, Volume 2A: Instruction Set Reference
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//! A-M (253666-052), 3.2 “FXSAVE”, specifically, the notes on the abridged
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//! FTW and recreating the FSAVE format, and AMD Architecture Programmer’s
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//! Manual, Volume 2: System Programming (24593-3.24), “FXSAVE Format for x87
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//! Tag Word”.
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//!
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//! \sa FsaveToFxsaveTagWord()
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//!
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//! \param[in] fsw The FPU status word, used to map logical \a st_mm registers
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//! to their physical counterparts. This can be taken from
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//! CPUContextX86::Fxsave::fsw.
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//! \param[in] fxsave_tag The abridged FPU tag word. This can be taken from
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//! CPUContextX86::Fxsave::ftw.
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//! \param[in] st_mm The floating-point registers in logical order. This can
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//! be taken from CPUContextX86::Fxsave::st_mm.
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//!
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//! \return The full FPU tag word.
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static uint16_t FxsaveToFsaveTagWord(
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uint16_t fsw, uint8_t fxsave_tag, const X87OrMMXRegister st_mm[8]);
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//! \brief Converts x87 floating-point tag words from `fsave` (full, 16-bit)
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//! to `fxsave` (abridged, 8-bit) form.
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//!
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//! This function performs the inverse operation of FxsaveToFsaveTagWord().
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//!
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//! \param[in] fsave_tag The full FPU tag word.
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//!
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//! \return The abridged FPU tag word.
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static uint8_t FsaveToFxsaveTagWord(uint16_t fsave_tag);
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// Integer registers.
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uint32_t eax;
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uint32_t ebx;
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uint32_t ecx;
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uint32_t edx;
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uint32_t edi; // destination index
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uint32_t esi; // source index
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uint32_t ebp; // base pointer
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uint32_t esp; // stack pointer
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uint32_t eip; // instruction pointer
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uint32_t eflags;
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uint16_t cs; // code segment selector
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uint16_t ds; // data segment selector
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uint16_t es; // extra segment selector
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uint16_t fs;
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uint16_t gs;
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uint16_t ss; // stack segment selector
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// Floating-point and vector registers.
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Fxsave fxsave;
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// Debug registers.
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uint32_t dr0;
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uint32_t dr1;
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uint32_t dr2;
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uint32_t dr3;
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uint32_t dr4; // obsolete, normally an alias for dr6
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uint32_t dr5; // obsolete, normally an alias for dr7
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uint32_t dr6;
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uint32_t dr7;
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};
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//! \brief A context structure carrying x86_64 CPU state.
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struct CPUContextX86_64 {
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using X87Register = CPUContextX86::X87Register;
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using X87OrMMXRegister = CPUContextX86::X87OrMMXRegister;
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using XMMRegister = CPUContextX86::XMMRegister;
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struct Fxsave {
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uint16_t fcw; // FPU control word
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uint16_t fsw; // FPU status word
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uint8_t ftw; // abridged FPU tag word
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uint8_t reserved_1;
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uint16_t fop; // FPU opcode
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union {
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// The expression of these union members is determined by the use of
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// fxsave/fxrstor or fxsave64/fxrstor64 (fxsaveq/fxrstorq). macOS and
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// Windows systems use the traditional fxsave/fxrstor structure.
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struct {
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// fxsave/fxrstor
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uint32_t fpu_ip; // FPU instruction pointer offset
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uint16_t fpu_cs; // FPU instruction pointer segment selector
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uint16_t reserved_2;
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uint32_t fpu_dp; // FPU data pointer offset
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uint16_t fpu_ds; // FPU data pointer segment selector
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uint16_t reserved_3;
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};
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struct {
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// fxsave64/fxrstor64 (fxsaveq/fxrstorq)
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uint64_t fpu_ip_64; // FPU instruction pointer
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uint64_t fpu_dp_64; // FPU data pointer
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};
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};
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uint32_t mxcsr; // multimedia extensions status and control register
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uint32_t mxcsr_mask; // valid bits in mxcsr
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X87OrMMXRegister st_mm[8];
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XMMRegister xmm[16];
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uint8_t reserved_4[48];
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uint8_t available[48];
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};
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// Integer registers.
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uint64_t rax;
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uint64_t rbx;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rdi; // destination index
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uint64_t rsi; // source index
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uint64_t rbp; // base pointer
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uint64_t rsp; // stack pointer
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t rip; // instruction pointer
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uint64_t rflags;
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uint16_t cs; // code segment selector
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uint16_t fs;
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uint16_t gs;
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// Floating-point and vector registers.
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Fxsave fxsave;
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// Debug registers.
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uint64_t dr0;
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uint64_t dr1;
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uint64_t dr2;
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uint64_t dr3;
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uint64_t dr4; // obsolete, normally an alias for dr6
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uint64_t dr5; // obsolete, normally an alias for dr7
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uint64_t dr6;
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uint64_t dr7;
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struct {
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// If 0 then none of the xsave areas are valid.
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uint64_t enabled_features;
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// CET_U registers if XSTATE_CET_U bit is set in enabled_features.
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struct {
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uint64_t cetmsr;
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uint64_t ssp;
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} cet_u;
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} xstate;
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};
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//! \brief A context structure carrying ARM CPU state.
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struct CPUContextARM {
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uint32_t regs[11];
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uint32_t fp; // r11
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uint32_t ip; // r12
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uint32_t sp; // r13
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uint32_t lr; // r14
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uint32_t pc; // r15
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uint32_t cpsr;
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struct {
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struct fp_reg {
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uint32_t sign1 : 1;
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uint32_t unused : 15;
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uint32_t sign2 : 1;
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uint32_t exponent : 14;
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uint32_t j : 1;
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uint32_t mantissa1 : 31;
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uint32_t mantisss0 : 32;
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} fpregs[8];
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uint32_t fpsr : 32;
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uint32_t fpcr : 32;
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uint8_t type[8];
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uint32_t init_flag;
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} fpa_regs;
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struct {
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uint64_t vfp[32];
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uint32_t fpscr;
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} vfp_regs;
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bool have_fpa_regs;
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bool have_vfp_regs;
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};
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//! \brief A context structure carrying ARM64 CPU state.
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struct CPUContextARM64 {
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uint64_t regs[31];
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uint64_t sp;
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uint64_t pc;
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uint32_t spsr;
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uint128_struct fpsimd[32];
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uint32_t fpsr;
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uint32_t fpcr;
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};
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//! \brief A context structure carrying MIPS CPU state.
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struct CPUContextMIPS {
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uint64_t regs[32];
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uint32_t mdlo;
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uint32_t mdhi;
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uint32_t cp0_epc;
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uint32_t cp0_badvaddr;
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uint32_t cp0_status;
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uint32_t cp0_cause;
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uint32_t hi[3];
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uint32_t lo[3];
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uint32_t dsp_control;
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union {
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double dregs[32];
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struct {
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float _fp_fregs;
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uint32_t _fp_pad;
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} fregs[32];
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} fpregs;
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uint32_t fpcsr;
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uint32_t fir;
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};
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//! \brief A context structure carrying MIPS64 CPU state.
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struct CPUContextMIPS64 {
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uint64_t regs[32];
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uint64_t mdlo;
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uint64_t mdhi;
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uint64_t cp0_epc;
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uint64_t cp0_badvaddr;
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uint64_t cp0_status;
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uint64_t cp0_cause;
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uint64_t hi[3];
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uint64_t lo[3];
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uint64_t dsp_control;
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union {
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double dregs[32];
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struct {
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float _fp_fregs;
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uint32_t _fp_pad;
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} fregs[32];
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} fpregs;
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uint64_t fpcsr;
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uint64_t fir;
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};
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//! \brief A context structure capable of carrying the context of any supported
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//! CPU architecture.
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struct CPUContext {
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//! \brief Returns the instruction pointer value from the context structure.
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//!
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//! This is a CPU architecture-independent method that is capable of
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//! recovering the instruction pointer from any supported CPU architecture’s
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//! context structure.
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uint64_t InstructionPointer() const;
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//! \brief Returns the stack pointer value from the context structure.
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//!
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//! This is a CPU architecture-independent method that is capable of
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//! recovering the stack pointer from any supported CPU architecture’s
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//! context structure.
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uint64_t StackPointer() const;
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//! \brief Returns the shadow stack pointer value from the context structure.
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//!
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//! This is a CPU architecture-independent method that is capable of
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//! recovering the shadow stack pointer from any supported CPU architecture’s
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//! context structure.
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uint64_t ShadowStackPointer() const;
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//! \brief Returns `true` if this context is for a 64-bit architecture.
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bool Is64Bit() const;
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//! \brief Returns `true` if this context has an active shadow stack pointer.
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bool HasShadowStack() const;
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//! \brief The CPU architecture of a context structure. This field controls
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//! the expression of the union.
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CPUArchitecture architecture;
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union {
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CPUContextX86* x86;
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CPUContextX86_64* x86_64;
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CPUContextARM* arm;
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CPUContextARM64* arm64;
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CPUContextMIPS* mipsel;
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CPUContextMIPS64* mips64;
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};
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};
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} // namespace crashpad
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#endif // CRASHPAD_SNAPSHOT_SNAPSHOT_CPU_CONTEXT_H_
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