473 lines
13 KiB
C++
473 lines
13 KiB
C++
/* BOARD.CPP : functions for autorouting */
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#include "fctsys.h"
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#include "common.h"
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#include "pcbnew.h"
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#include "autorout.h"
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#include "cell.h"
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/*
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* Calculates nrows and ncols, dimensions of the matrix representation of BOARD
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* for routing and automatic calculation of area.
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*/
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bool MATRIX_ROUTING_HEAD::ComputeMatrixSize( BOARD* aPcb )
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{
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aPcb->ComputeBoundingBox();
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/* The boundary box must have its start point on routing grid: */
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aPcb->m_BoundaryBox.m_Pos.x -= aPcb->m_BoundaryBox.m_Pos.x % m_GridRouting;
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aPcb->m_BoundaryBox.m_Pos.y -= aPcb->m_BoundaryBox.m_Pos.y % m_GridRouting;
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m_BrdBox = aPcb->m_BoundaryBox;
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/* The boundary box must have its end point on routing grid: */
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wxPoint end = m_BrdBox.GetEnd();
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end.x -= end.x % m_GridRouting;
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end.x += m_GridRouting;
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end.y -= end.y % m_GridRouting;
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end.y += m_GridRouting;
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aPcb->m_BoundaryBox.SetEnd( end );
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m_BrdBox.SetEnd(end);
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m_Nrows = Nrows = m_BrdBox.m_Size.y / m_GridRouting;
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m_Ncols = Ncols = m_BrdBox.m_Size.x / m_GridRouting;
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/* get a small margin for memory allocation: */
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Ncols += 1; Nrows += 1;
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return true;
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}
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/* class MATRIX_ROUTING_HEAD
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*/
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MATRIX_ROUTING_HEAD::MATRIX_ROUTING_HEAD()
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{
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m_BoardSide[0] = m_BoardSide[1] = NULL;
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m_DistSide[0] = m_DistSide[1] = NULL;
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m_DirSide[0] = m_DirSide[1] = NULL;
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m_InitBoardDone = false;
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m_Layers = MAX_SIDES_COUNT;
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m_Nrows = m_Ncols = 0;
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m_MemSize = 0;
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}
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MATRIX_ROUTING_HEAD::~MATRIX_ROUTING_HEAD()
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{
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}
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/* initialize the data structures
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* returns the RAM size used, or -1 if default
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*/
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int MATRIX_ROUTING_HEAD::InitBoard()
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{
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int ii, kk;
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if( Nrows <= 0 || Ncols <= 0 )
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return 0;
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m_Nrows = Nrows;
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m_Ncols = Ncols;
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m_InitBoardDone = true; /* we have been called */
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ii = (Nrows + 1) * (Ncols + 1);
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for( kk = 0; kk < m_Layers; kk++ )
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{
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m_BoardSide[kk] = NULL;
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m_DistSide[kk] = NULL;
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m_DirSide[kk] = NULL;
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/* allocate Board & initialize everything to empty */
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m_BoardSide[kk] = (MATRIX_CELL*) MyZMalloc( ii * sizeof(MATRIX_CELL) );
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if( m_BoardSide[kk] == NULL )
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return -1;
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/***** allocate Distances *****/
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m_DistSide[kk] = (DIST_CELL*) MyZMalloc( ii * sizeof(DIST_CELL) );
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if( m_DistSide[kk] == NULL )
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return -1;
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/***** allocate Dir (chars) *****/
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m_DirSide[kk] = (char*) MyZMalloc( ii );
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if( m_DirSide[kk] == NULL )
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return -1;
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}
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m_MemSize = m_Layers * ii * ( sizeof(MATRIX_CELL) + sizeof(DIST_CELL) + sizeof(char) );
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return m_MemSize;
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}
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void MATRIX_ROUTING_HEAD::UnInitBoard()
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{
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int ii;
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m_InitBoardDone = false;
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for( ii = 0; ii < MAX_SIDES_COUNT; ii++ )
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{
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/***** de-allocate Dir matrix *****/
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if( m_DirSide[ii] )
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{
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MyFree( m_DirSide[ii] ); m_DirSide[ii] = NULL;
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}
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/***** de-allocate Distances matrix *****/
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if( m_DistSide[ii] )
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{
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MyFree( m_DistSide[ii] ); m_DistSide[ii] = NULL;
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}
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/**** de-allocate cells matrix *****/
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if( m_BoardSide[ii] )
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{
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MyFree( m_BoardSide[ii] ); m_BoardSide[ii] = NULL;
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}
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}
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m_Nrows = m_Ncols = 0;
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}
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/* Initialize the cell board is set and VIA_IMPOSSIBLE HOLE according to
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* the setbacks
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* The elements of net_code = net_code will not be occupied as places
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* but only VIA_IMPOSSIBLE
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* For single-sided Routing 1:
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* BOTTOM side is used and Route_Layer_BOTTOM = Route_Layer_TOP
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*
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* According to the bits = 1 parameter flag:
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* If FORCE_PADS: all pads will be placed even those same net_code.
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*/
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void PlaceCells( BOARD* aPcb, int net_code, int flag )
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{
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int ux0 = 0, uy0 = 0, ux1, uy1, dx, dy;
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int marge, via_marge;
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int masque_layer;
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// use the default NETCLASS?
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NETCLASS* nc = aPcb->m_NetClasses.GetDefault();
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int trackWidth = nc->GetTrackWidth();
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int clearance = nc->GetClearance();
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int viaSize = nc->GetViaDiameter();
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marge = clearance + (trackWidth / 2);
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via_marge = clearance + (viaSize / 2);
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// Place PADS on matrix routing:
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for( unsigned i = 0; i < aPcb->GetPadsCount(); ++i )
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{
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D_PAD* pad = aPcb->m_NetInfo->GetPad( i );
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if( net_code != pad->GetNet() || (flag & FORCE_PADS) )
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{
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Place_1_Pad_Board( aPcb, pad, HOLE, marge, WRITE_CELL );
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}
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Place_1_Pad_Board( aPcb, pad, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
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}
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// Place outlines of modules on matrix routing, if they are on a copper layer
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// or on the edge layer
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TRACK tmpSegm( NULL ); // A dummy track used to create segments.
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for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
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{
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for( BOARD_ITEM* item = module->m_Drawings; item; item = item->Next() )
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{
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switch( item->Type() )
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{
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case TYPE_EDGE_MODULE:
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{
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EDGE_MODULE* edge = (EDGE_MODULE*) item;
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tmpSegm.SetLayer( edge->GetLayer() );
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if( tmpSegm.GetLayer() == EDGE_N )
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tmpSegm.SetLayer( -1 );
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tmpSegm.m_Start = edge->m_Start;
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tmpSegm.m_End = edge->m_End;
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tmpSegm.m_Shape = edge->m_Shape;
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tmpSegm.m_Width = edge->m_Width;
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tmpSegm.m_Param = edge->m_Angle;
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tmpSegm.SetNet( -1 );
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TraceSegmentPcb( aPcb, &tmpSegm, HOLE, marge, WRITE_CELL );
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TraceSegmentPcb( aPcb, &tmpSegm, VIA_IMPOSSIBLE, via_marge,
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WRITE_OR_CELL );
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}
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break;
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default:
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break;
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}
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}
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}
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// Place board outlines and texts on copper layers:
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for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
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{
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switch( item->Type() )
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{
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case TYPE_DRAWSEGMENT:
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{
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DRAWSEGMENT* DrawSegm;
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int type_cell = HOLE;
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DrawSegm = (DRAWSEGMENT*) item;
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tmpSegm.SetLayer( DrawSegm->GetLayer() );
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if( DrawSegm->GetLayer() == EDGE_N )
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{
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tmpSegm.SetLayer( -1 );
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type_cell |= CELL_is_EDGE;
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}
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tmpSegm.m_Start = DrawSegm->m_Start;
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tmpSegm.m_End = DrawSegm->m_End;
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tmpSegm.m_Shape = DrawSegm->m_Shape;
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tmpSegm.m_Width = DrawSegm->m_Width;
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tmpSegm.m_Param = DrawSegm->m_Angle;
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tmpSegm.SetNet( -1 );
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TraceSegmentPcb( aPcb, &tmpSegm, type_cell, marge, WRITE_CELL );
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}
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break;
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case TYPE_TEXTE:
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{
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TEXTE_PCB* PtText;
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PtText = (TEXTE_PCB*) item;
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if( PtText->GetLength() == 0 )
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break;
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EDA_RECT textbox = PtText->GetTextBox( -1 );
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ux0 = textbox.GetX(); uy0 = textbox.GetY();
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dx = textbox.GetWidth();
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dy = textbox.GetHeight();
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/* Put bounding box (rectangle) on matrix */
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dx /= 2;
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dy /= 2;
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ux1 = ux0 + dx;
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uy1 = uy0 + dy;
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ux0 -= dx;
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uy0 -= dy;
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masque_layer = g_TabOneLayerMask[PtText->GetLayer()];
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TraceFilledRectangle( aPcb, ux0 - marge, uy0 - marge, ux1 + marge,
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uy1 + marge, (int) (PtText->m_Orient),
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masque_layer, HOLE, WRITE_CELL );
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TraceFilledRectangle( aPcb, ux0 - via_marge, uy0 - via_marge,
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ux1 + via_marge, uy1 + via_marge,
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(int) (PtText->m_Orient),
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masque_layer, VIA_IMPOSSIBLE, WRITE_OR_CELL );
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}
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break;
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default:
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break;
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}
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}
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/* Put tracks and vias on matrix */
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for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
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{
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if( net_code == track->GetNet() )
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continue;
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TraceSegmentPcb( aPcb, track, HOLE, marge, WRITE_CELL );
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TraceSegmentPcb( aPcb, track, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
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}
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}
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int Build_Work( BOARD* Pcb )
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{
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RATSNEST_ITEM* pt_rats;
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D_PAD* pt_pad;
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int r1, r2, c1, c2, current_net_code;
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RATSNEST_ITEM* pt_ch;
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int demi_pas = Board.m_GridRouting / 2;
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wxString msg;
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InitWork(); /* clear work list */
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Ntotal = 0;
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for( unsigned ii = 0; ii < Pcb->GetRatsnestsCount(); ii++ )
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{
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pt_rats = &Pcb->m_FullRatsnest[ii];
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/* We consider her only ratsnets that are active ( obviously not yet routed)
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* and routables (that are not yet attempt to be routed and fail
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*/
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if( (pt_rats->m_Status & CH_ACTIF) == 0 )
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continue;
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if( pt_rats->m_Status & CH_UNROUTABLE )
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continue;
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if( (pt_rats->m_Status & CH_ROUTE_REQ) == 0 )
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continue;
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pt_pad = pt_rats->m_PadStart;
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current_net_code = pt_pad->GetNet();
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pt_ch = pt_rats;
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r1 = ( pt_pad->GetPosition().y - Pcb->m_BoundaryBox.m_Pos.y
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+ demi_pas ) / Board.m_GridRouting;
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if( r1 < 0 || r1 >= Nrows )
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{
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msg.Printf( wxT( "error : row = %d ( padY %d pcbY %d) " ), r1,
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pt_pad->GetPosition().y, Pcb->m_BoundaryBox.m_Pos.y );
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wxMessageBox( msg );
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return 0;
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}
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c1 = ( pt_pad->GetPosition().x - Pcb->m_BoundaryBox.m_Pos.x
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+ demi_pas ) / Board.m_GridRouting;
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if( c1 < 0 || c1 >= Ncols )
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{
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msg.Printf( wxT( "error : col = %d ( padX %d pcbX %d) " ), c1,
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pt_pad->GetPosition().x, Pcb->m_BoundaryBox.m_Pos.x );
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wxMessageBox( msg );
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return 0;
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}
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pt_pad = pt_rats->m_PadEnd;
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r2 = ( pt_pad->GetPosition().y - Pcb->m_BoundaryBox.m_Pos.y
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+ demi_pas ) / Board.m_GridRouting;
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if( r2 < 0 || r2 >= Nrows )
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{
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msg.Printf( wxT( "error : row = %d ( padY %d pcbY %d) " ), r2,
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pt_pad->GetPosition().y, Pcb->m_BoundaryBox.m_Pos.y );
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wxMessageBox( msg );
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return 0;
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}
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c2 = ( pt_pad->GetPosition().x - Pcb->m_BoundaryBox.m_Pos.x
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+ demi_pas ) / Board.m_GridRouting;
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if( c2 < 0 || c2 >= Ncols )
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{
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msg.Printf( wxT( "error : col = %d ( padX %d pcbX %d) " ), c2,
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pt_pad->GetPosition().x, Pcb->m_BoundaryBox.m_Pos.x );
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wxMessageBox( msg );
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return 0;
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}
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SetWork( r1, c1, current_net_code, r2, c2, pt_ch, 0 );
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Ntotal++;
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}
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SortWork();
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return Ntotal;
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}
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/* return the value stored in a cell
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*/
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MATRIX_CELL GetCell( int aRow, int aCol, int aSide )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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return p[aRow * Ncols + aCol];
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}
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/* basic cell operation : WRITE operation
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*/
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void SetCell( int aRow, int aCol, int aSide, MATRIX_CELL x )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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p[aRow * Ncols + aCol] = x;
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}
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/* basic cell operation : OR operation
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*/
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void OrCell( int aRow, int aCol, int aSide, MATRIX_CELL x )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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p[aRow * Ncols + aCol] |= x;
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}
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/* basic cell operation : XOR operation
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*/
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void XorCell( int aRow, int aCol, int aSide, MATRIX_CELL x )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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p[aRow * Ncols + aCol] ^= x;
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}
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/* basic cell operation : AND operation
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*/
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void AndCell( int aRow, int aCol, int aSide, MATRIX_CELL x )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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p[aRow * Ncols + aCol] &= x;
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}
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/* basic cell operation : ADD operation
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*/
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void AddCell( int aRow, int aCol, int aSide, MATRIX_CELL x )
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{
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MATRIX_CELL* p;
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p = Board.m_BoardSide[aSide];
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p[aRow * Ncols + aCol] += x;
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}
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/* fetch distance cell */
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DIST_CELL GetDist( int aRow, int aCol, int aSide ) /* fetch distance cell */
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{
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DIST_CELL* p;
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p = Board.m_DistSide[aSide];
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return p[aRow * Ncols + aCol];
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}
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/* store distance cell */
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void SetDist( int aRow, int aCol, int aSide, DIST_CELL x )
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{
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DIST_CELL* p;
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p = Board.m_DistSide[aSide];
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p[aRow * Ncols + aCol] = x;
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}
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/* fetch direction cell */
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int GetDir( int aRow, int aCol, int aSide )
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{
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DIR_CELL* p;
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p = Board.m_DirSide[aSide];
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return (int) (p[aRow * Ncols + aCol]);
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}
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/* store direction cell */
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void SetDir( int aRow, int aCol, int aSide, int x )
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{
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DIR_CELL* p;
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p = Board.m_DirSide[aSide];
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p[aRow * Ncols + aCol] = (char) x;
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}
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