Roberto Fernandez Bautista ac3ade874e CADSTAR PCB: Set Copper-to-Hole clearance as 0 ... Testing suggests that CADSTAR doesn't actually have any clearance to the hole (other than electrical clearance to the barrel of the padstack/ viastack). This removes a large amount of DRC violations on imported designs.		2021-10-10 00:20:13 +01:00
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altium	Clear numbers from non-numberable pads and don't run DRC on them.	2021-08-24 01:03:06 +01:00
cadstar	CADSTAR PCB: Set Copper-to-Hole clearance as 0	2021-10-10 00:20:13 +01:00
common	Rename layer ids file.	2021-07-29 16:03:25 +01:00
eagle	Eagle doesn't use netclass clearance so make them the board clearance.	2021-09-20 21:31:19 +01:00
fabmaster	We don't keep a CHANGELOG.TXT	2021-10-05 19:46:53 -07:00
geda	Clear numbers from non-numberable pads and don't run DRC on them.	2021-08-24 01:03:06 +01:00
kicad	Clean up unused variable usage	2021-10-05 10:00:30 -07:00
legacy	Clean up unused variable usage	2021-10-05 10:00:30 -07:00
pcad	We don't keep a CHANGELOG.TXT	2021-10-05 19:46:53 -07:00