160 lines
4.5 KiB
C++
160 lines
4.5 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2020 KiCad Developers, see change_log.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef DRC_RULE_PROTO_H
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#define DRC_RULE_PROTO_H
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#include <core/typeinfo.h>
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#include <core/optional.h>
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#include <core/minoptmax.h>
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#include <layer_ids.h>
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#include <netclass.h>
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#include <libeval_compiler/libeval_compiler.h>
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#include <wx/intl.h>
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class BOARD_ITEM;
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class PCB_EXPR_UCODE;
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class DRC_CONSTRAINT;
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class DRC_RULE_CONDITION;
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enum DRC_CONSTRAINT_T
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{
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NULL_CONSTRAINT = 0,
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CLEARANCE_CONSTRAINT,
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HOLE_CLEARANCE_CONSTRAINT,
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HOLE_TO_HOLE_CONSTRAINT,
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EDGE_CLEARANCE_CONSTRAINT,
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HOLE_SIZE_CONSTRAINT,
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COURTYARD_CLEARANCE_CONSTRAINT,
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SILK_CLEARANCE_CONSTRAINT,
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TRACK_WIDTH_CONSTRAINT,
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ANNULAR_WIDTH_CONSTRAINT,
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DISALLOW_CONSTRAINT,
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VIA_DIAMETER_CONSTRAINT,
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LENGTH_CONSTRAINT,
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SKEW_CONSTRAINT,
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DIFF_PAIR_GAP_CONSTRAINT,
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DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT,
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DIFF_PAIR_INTRA_SKEW_CONSTRAINT,
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VIA_COUNT_CONSTRAINT
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};
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enum DRC_DISALLOW_T
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{
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DRC_DISALLOW_VIAS = (1 << 0),
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DRC_DISALLOW_MICRO_VIAS = (1 << 1),
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DRC_DISALLOW_BB_VIAS = (1 << 2),
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DRC_DISALLOW_TRACKS = (1 << 3),
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DRC_DISALLOW_PADS = (1 << 4),
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DRC_DISALLOW_ZONES = (1 << 5),
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DRC_DISALLOW_TEXTS = (1 << 6),
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DRC_DISALLOW_GRAPHICS = (1 << 7),
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DRC_DISALLOW_HOLES = (1 << 8),
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DRC_DISALLOW_FOOTPRINTS = (1 << 9)
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};
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class DRC_RULE
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{
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public:
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DRC_RULE();
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virtual ~DRC_RULE();
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virtual bool AppliesTo( const BOARD_ITEM* a, const BOARD_ITEM* b = nullptr ) const
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{
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return true;
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};
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void AddConstraint( DRC_CONSTRAINT& aConstraint );
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OPT<DRC_CONSTRAINT> FindConstraint( DRC_CONSTRAINT_T aType );
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public:
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bool m_Unary;
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bool m_Implicit;
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wxString m_Name;
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wxString m_LayerSource;
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LSET m_LayerCondition;
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DRC_RULE_CONDITION* m_Condition;
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std::vector<DRC_CONSTRAINT> m_Constraints;
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};
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class DRC_CONSTRAINT
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{
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public:
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DRC_CONSTRAINT( DRC_CONSTRAINT_T aType = NULL_CONSTRAINT,
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const wxString& aName = wxEmptyString ) :
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m_Type( aType ),
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m_Value(),
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m_DisallowFlags( 0 ),
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m_name( aName ),
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m_parentRule( nullptr )
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{
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}
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bool IsNull() const
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{
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return m_Type == NULL_CONSTRAINT;
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}
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const MINOPTMAX<int>& GetValue() const { return m_Value; }
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MINOPTMAX<int>& Value() { return m_Value; }
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void SetParentRule( DRC_RULE *aParentRule ) { m_parentRule = aParentRule; }
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DRC_RULE* GetParentRule() const { return m_parentRule; }
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void SetName( const wxString& aName ) { m_name = aName; }
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wxString GetName() const
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{
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if( m_parentRule )
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{
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if( m_parentRule->m_Implicit )
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return m_parentRule->m_Name;
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else
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return wxString::Format( _( "rule %s" ), m_parentRule->m_Name );
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}
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return m_name;
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}
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public:
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DRC_CONSTRAINT_T m_Type;
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MINOPTMAX<int> m_Value;
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int m_DisallowFlags;
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private:
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wxString m_name; // For just-in-time constraints
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DRC_RULE* m_parentRule; // For constraints found in rules
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};
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const DRC_CONSTRAINT* GetConstraint( const BOARD_ITEM* aItem, const BOARD_ITEM* bItem,
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int aConstraint, PCB_LAYER_ID aLayer,
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wxString* aRuleName = nullptr );
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#endif // DRC_RULE_H
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