96 lines
3.6 KiB
C++
96 lines
3.6 KiB
C++
// Copyright 2018 The Crashpad Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "snapshot/fuchsia/cpu_context_fuchsia.h"
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#include <string.h>
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namespace crashpad {
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namespace internal {
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#if defined(ARCH_CPU_X86_64)
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void InitializeCPUContextX86_64_NoFloatingPoint(
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const zx_thread_state_general_regs_t& thread_context,
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CPUContextX86_64* context) {
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memset(context, 0, sizeof(*context));
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context->rax = thread_context.rax;
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context->rbx = thread_context.rbx;
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context->rcx = thread_context.rcx;
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context->rdx = thread_context.rdx;
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context->rdi = thread_context.rdi;
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context->rsi = thread_context.rsi;
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context->rbp = thread_context.rbp;
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context->rsp = thread_context.rsp;
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context->r8 = thread_context.r8;
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context->r9 = thread_context.r9;
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context->r10 = thread_context.r10;
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context->r11 = thread_context.r11;
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context->r12 = thread_context.r12;
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context->r13 = thread_context.r13;
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context->r14 = thread_context.r14;
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context->r15 = thread_context.r15;
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context->rip = thread_context.rip;
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context->rflags = thread_context.rflags;
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}
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#elif defined(ARCH_CPU_ARM64)
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void InitializeCPUContextARM64(
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const zx_thread_state_general_regs_t& thread_context,
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const zx_thread_state_vector_regs_t& vector_context,
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CPUContextARM64* context) {
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memset(context, 0, sizeof(*context));
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// Fuchsia stores the link register (x30) on its own while Crashpad stores it
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// with the other general purpose x0-x28 and x29 frame pointer registers. So
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// we expect the size and number of elements to be off by one unit.
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static_assert(sizeof(context->regs) - sizeof(context->regs[30]) ==
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sizeof(thread_context.r),
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"registers size mismatch");
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static_assert((sizeof(context->regs) - sizeof(context->regs[30])) /
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sizeof(context->regs[0]) ==
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sizeof(thread_context.r) / sizeof(thread_context.r[0]),
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"registers number of elements mismatch");
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memcpy(&context->regs, &thread_context.r, sizeof(thread_context.r));
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context->regs[30] = thread_context.lr;
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context->sp = thread_context.sp;
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context->pc = thread_context.pc;
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// Only the NZCV flags (bits 31 to 28 respectively) of the cpsr register are
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// readable and writable by userland on ARM64.
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constexpr uint32_t kNZCV = 0xf0000000;
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// Fuchsia uses the old "cspr" terminology from armv7 while Crashpad uses the
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// new "spsr" terminology for armv8.
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context->spsr = thread_context.cpsr & kNZCV;
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if (thread_context.cpsr >
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std::numeric_limits<decltype(context->spsr)>::max()) {
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LOG(WARNING) << "cpsr truncation: we only expect the first 32 bits to be "
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"set in the cpsr";
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}
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context->spsr =
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static_cast<decltype(context->spsr)>(thread_context.cpsr) & kNZCV;
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context->fpcr = vector_context.fpcr;
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context->fpsr = vector_context.fpsr;
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static_assert(sizeof(context->fpsimd) == sizeof(vector_context.v),
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"registers size mismatch");
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memcpy(&context->fpsimd, &vector_context.v, sizeof(vector_context.v));
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}
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#endif // ARCH_CPU_X86_64
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} // namespace internal
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} // namespace crashpad
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