320 lines
10 KiB
C++
320 lines
10 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <pcb_track.h>
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#include <pad.h>
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#include <footprint.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <macros.h>
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#include <convert_basic_shapes_to_polygon.h>
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#include <board_design_settings.h>
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/*
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Via/pad annular ring width test. Checks if there's sufficient copper ring around
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PTH/NPTH holes (vias/pads)
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Errors generated:
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- DRCE_ANNULAR_WIDTH
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Todo:
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- check pad holes too.
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- pad stack support (different IAR/OAR values depending on layer)
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*/
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class DRC_TEST_PROVIDER_ANNULAR_WIDTH : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_ANNULAR_WIDTH()
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{
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}
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virtual ~DRC_TEST_PROVIDER_ANNULAR_WIDTH()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "annular_width" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests pad/via annular rings" );
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}
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};
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bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) )
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{
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reportAux( wxT( "Annular width violations ignored. Skipping check." ) );
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return true; // continue with other tests
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}
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const int progressDelta = 500;
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if( !m_drcEngine->HasRulesForConstraintType( ANNULAR_WIDTH_CONSTRAINT ) )
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{
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reportAux( wxT( "No annular width constraints found. Tests not run." ) );
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return true; // continue with other tests
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}
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if( !reportPhase( _( "Checking pad & via annular rings..." ) ) )
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return false; // DRC cancelled
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int maxError = m_drcEngine->GetBoard()->GetDesignSettings().m_MaxError;
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auto calcEffort =
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[]( BOARD_ITEM* item )
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{
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switch( item->Type() )
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{
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case PCB_VIA_T:
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return 1;
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case PCB_PAD_T:
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{
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PAD* pad = static_cast<PAD*>( item );
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if( !pad->HasHole() || pad->GetAttribute() != PAD_ATTRIB::PTH )
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return 0;
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if( pad->GetOffset() == VECTOR2I( 0, 0 ) )
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{
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switch( pad->GetShape() )
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{
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case PAD_SHAPE::CHAMFERED_RECT:
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if( pad->GetChamferRectRatio() > 0.30 )
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break;
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KI_FALLTHROUGH;
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case PAD_SHAPE::CIRCLE:
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case PAD_SHAPE::OVAL:
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case PAD_SHAPE::RECT:
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case PAD_SHAPE::ROUNDRECT:
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return 1;
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default:
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break;
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}
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}
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return 5;
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}
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default:
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return 0;
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}
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};
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auto checkAnnularWidth =
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) )
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return false;
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int annularWidth = 0;
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switch( item->Type() )
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{
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case PCB_VIA_T:
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{
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PCB_VIA* via = static_cast<PCB_VIA*>( item );
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annularWidth = ( via->GetWidth() - via->GetDrillValue() ) / 2;
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break;
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}
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case PCB_PAD_T:
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{
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PAD* pad = static_cast<PAD*>( item );
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bool handled = false;
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if( !pad->HasHole() || pad->GetAttribute() != PAD_ATTRIB::PTH )
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return true;
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if( pad->GetOffset() == VECTOR2I( 0, 0 ) )
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{
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switch( pad->GetShape() )
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{
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case PAD_SHAPE::CHAMFERED_RECT:
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if( pad->GetChamferRectRatio() > 0.30 )
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break;
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KI_FALLTHROUGH;
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case PAD_SHAPE::CIRCLE:
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case PAD_SHAPE::OVAL:
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case PAD_SHAPE::RECT:
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case PAD_SHAPE::ROUNDRECT:
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annularWidth = std::min( pad->GetSizeX() - pad->GetDrillSizeX(),
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pad->GetSizeY() - pad->GetDrillSizeY() ) / 2;
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handled = true;
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break;
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default:
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break;
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}
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}
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if( !handled )
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{
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// Slow (but general purpose) method.
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SHAPE_POLY_SET padOutline;
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pad->TransformShapeWithClearanceToPolygon( padOutline, UNDEFINED_LAYER, 0,
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maxError, ERROR_INSIDE );
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if( !padOutline.Collide( pad->GetPosition() ) )
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{
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// Hole outside pad
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annularWidth = 0;
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}
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else
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{
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std::shared_ptr<SHAPE_SEGMENT> slot = pad->GetEffectiveHoleShape();
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// Disable is-inside test in SquaredDistance
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padOutline.Outline( 0 ).SetClosed( false );
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SEG::ecoord dist_sq = padOutline.SquaredDistance( slot->GetSeg() );
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annularWidth = sqrt( dist_sq ) - slot->GetWidth() / 2;
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}
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}
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break;
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}
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default:
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return true;
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}
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// PADSTACKS TODO: once we have padstacks we'll need to run this per-layer....
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auto constraint = m_drcEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, item, nullptr,
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UNDEFINED_LAYER );
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int v_min = 0;
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int v_max = 0;
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bool fail_min = false;
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bool fail_max = false;
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
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return true;
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if( constraint.Value().HasMin() )
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{
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v_min = constraint.Value().Min();
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fail_min = annularWidth < v_min;
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}
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if( constraint.Value().HasMax() )
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{
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v_max = constraint.Value().Max();
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fail_max = annularWidth > v_max;
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}
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if( fail_min || fail_max )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULAR_WIDTH );
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wxString msg;
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if( fail_min )
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{
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msg.Printf( _( "(%s min annular width %s; actual %s)" ),
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constraint.GetName(),
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MessageTextFromValue( userUnits(), v_min ),
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MessageTextFromValue( userUnits(), annularWidth ) );
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}
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if( fail_max )
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{
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msg.Printf( _( "(%s max annular width %s; actual %s)" ),
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constraint.GetName(),
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MessageTextFromValue( userUnits(), v_max ),
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MessageTextFromValue( userUnits(), annularWidth ) );
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}
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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drcItem->SetItems( item );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drcItem, item->GetPosition(), item->GetLayer() );
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}
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return true;
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};
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BOARD* board = m_drcEngine->GetBoard();
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size_t ii = 0;
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size_t total = 0;
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for( PCB_TRACK* item : board->Tracks() )
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total += calcEffort( item );
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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total += calcEffort( pad );
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}
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for( PCB_TRACK* item : board->Tracks() )
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{
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ii += calcEffort( item );
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if( !reportProgress( ii, total, progressDelta ) )
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return false; // DRC cancelled
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if( !checkAnnularWidth( item ) )
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break;
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}
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for( FOOTPRINT* footprint : board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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ii += calcEffort( pad );
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if( !reportProgress( ii, total, progressDelta ) )
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return false; // DRC cancelled
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if( !checkAnnularWidth( pad ) )
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break;
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}
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}
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reportRuleStatistics();
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_ANNULAR_WIDTH> dummy;
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}
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