789 lines
28 KiB
C++
789 lines
28 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <board_design_settings.h>
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#include <board_connected_item.h>
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#include <footprint.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <pcb_text.h>
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#include <zone.h>
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#include <geometry/seg.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include <drc/drc_rtree.h>
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/*
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Solder mask tests. Checks for silkscreen which is clipped by mask openings and for bridges
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between mask apertures with different nets.
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Errors generated:
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- DRCE_SILK_CLEARANCE
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- DRCE_SOLDERMASK_BRIDGE
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*/
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class DRC_TEST_PROVIDER_SOLDER_MASK : public ::DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_SOLDER_MASK ():
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m_board( nullptr ),
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m_webWidth( 0 ),
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m_maxError( 0 ),
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m_largestClearance( 0 )
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{
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m_bridgeRule.m_Name = _( "board setup solder mask min width" );
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}
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virtual ~DRC_TEST_PROVIDER_SOLDER_MASK()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "solder_mask_issues" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests for silkscreen being clipped by solder mask and copper being exposed "
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"by mask apertures of other nets" );
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}
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private:
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void addItemToRTrees( BOARD_ITEM* aItem );
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void buildRTrees();
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void testSilkToMaskClearance();
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void testMaskBridges();
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void testItemAgainstItems( BOARD_ITEM* aItem, const BOX2I& aItemBBox,
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PCB_LAYER_ID aRefLayer, PCB_LAYER_ID aTargetLayer );
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void testMaskItemAgainstZones( BOARD_ITEM* item, const BOX2I& itemBBox,
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PCB_LAYER_ID refLayer, PCB_LAYER_ID targetLayer );
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bool checkMaskAperture( BOARD_ITEM* aMaskItem, BOARD_ITEM* aTestItem, PCB_LAYER_ID aTestLayer,
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int aTestNet, BOARD_ITEM** aCollidingItem );
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bool checkItemMask( BOARD_ITEM* aMaskItem, int aTestNet );
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private:
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DRC_RULE m_bridgeRule;
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BOARD* m_board;
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int m_webWidth;
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int m_maxError;
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int m_largestClearance;
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std::unique_ptr<DRC_RTREE> m_fullSolderMaskRTree;
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std::unique_ptr<DRC_RTREE> m_itemTree;
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std::unordered_map<PTR_PTR_CACHE_KEY, LSET> m_checkedPairs;
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// Shapes used to define solder mask apertures don't have nets, so we assign them the
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// first object+net that bridges their aperture (after which any other nets will generate
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// violations).
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std::unordered_map<PTR_LAYER_CACHE_KEY, std::pair<BOARD_ITEM*, int>> m_maskApertureNetMap;
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};
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void DRC_TEST_PROVIDER_SOLDER_MASK::addItemToRTrees( BOARD_ITEM* aItem )
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{
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ZONE* solderMask = m_board->m_SolderMaskBridges;
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if( aItem->Type() == PCB_ZONE_T )
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{
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ZONE* zone = static_cast<ZONE*>( aItem );
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for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
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{
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if( zone->IsOnLayer( layer ) )
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{
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solderMask->GetFill( layer )->BooleanAdd( *zone->GetFilledPolysList( layer ),
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SHAPE_POLY_SET::PM_FAST );
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}
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}
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}
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else if( aItem->Type() == PCB_PAD_T )
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{
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for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
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{
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if( aItem->IsOnLayer( layer ) )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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int clearance = ( m_webWidth / 2 ) + pad->GetSolderMaskExpansion();
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aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
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m_maxError, ERROR_OUTSIDE );
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m_itemTree->Insert( aItem, layer, m_largestClearance );
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}
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}
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}
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else if( aItem->Type() == PCB_VIA_T )
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{
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for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
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{
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if( aItem->IsOnLayer( layer ) )
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{
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PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
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int clearance = ( m_webWidth / 2 ) + via->GetSolderMaskExpansion();
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via->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer, clearance,
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m_maxError, ERROR_OUTSIDE );
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m_itemTree->Insert( aItem, layer, m_largestClearance );
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}
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}
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}
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else if( aItem->Type() == PCB_FIELD_T || aItem->Type() == PCB_TEXT_T )
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{
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for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
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{
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if( aItem->IsOnLayer( layer ) )
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{
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const PCB_TEXT* text = static_cast<const PCB_TEXT*>( aItem );
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text->TransformTextToPolySet( *solderMask->GetFill( layer ),
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m_webWidth / 2, m_maxError, ERROR_OUTSIDE );
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m_itemTree->Insert( aItem, layer, m_largestClearance );
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}
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}
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}
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else
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{
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for( PCB_LAYER_ID layer : { F_Mask, B_Mask } )
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{
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if( aItem->IsOnLayer( layer ) )
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{
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aItem->TransformShapeToPolygon( *solderMask->GetFill( layer ), layer,
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m_webWidth / 2, m_maxError, ERROR_OUTSIDE );
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m_itemTree->Insert( aItem, layer, m_largestClearance );
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}
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}
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}
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}
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void DRC_TEST_PROVIDER_SOLDER_MASK::buildRTrees()
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{
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ZONE* solderMask = m_board->m_SolderMaskBridges;
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LSET layers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
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const size_t progressDelta = 500;
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int count = 0;
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int ii = 0;
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solderMask->GetFill( F_Mask )->RemoveAllContours();
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solderMask->GetFill( B_Mask )->RemoveAllContours();
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m_fullSolderMaskRTree = std::make_unique<DRC_RTREE>();
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m_itemTree = std::make_unique<DRC_RTREE>();
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forEachGeometryItem( s_allBasicItems, layers,
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[&]( BOARD_ITEM* item ) -> bool
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{
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++count;
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return true;
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} );
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forEachGeometryItem( s_allBasicItems, layers,
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( !reportProgress( ii++, count, progressDelta ) )
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return false;
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addItemToRTrees( item );
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return true;
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} );
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solderMask->GetFill( F_Mask )->Simplify( SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
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solderMask->GetFill( B_Mask )->Simplify( SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
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solderMask->GetFill( F_Mask )->Deflate( m_webWidth / 2, CORNER_STRATEGY::CHAMFER_ALL_CORNERS,
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m_maxError );
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solderMask->GetFill( B_Mask )->Deflate( m_webWidth / 2, CORNER_STRATEGY::CHAMFER_ALL_CORNERS,
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m_maxError );
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solderMask->SetFillFlag( F_Mask, true );
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solderMask->SetFillFlag( B_Mask, true );
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solderMask->SetIsFilled( true );
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solderMask->CacheTriangulation();
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m_fullSolderMaskRTree->Insert( solderMask, F_Mask );
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m_fullSolderMaskRTree->Insert( solderMask, B_Mask );
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m_checkedPairs.clear();
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}
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void DRC_TEST_PROVIDER_SOLDER_MASK::testSilkToMaskClearance()
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{
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LSET silkLayers = { 2, F_SilkS, B_SilkS };
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const size_t progressDelta = 250;
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int count = 0;
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int ii = 0;
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forEachGeometryItem( s_allBasicItems, silkLayers,
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[&]( BOARD_ITEM* item ) -> bool
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{
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++count;
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return true;
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} );
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forEachGeometryItem( s_allBasicItems, silkLayers,
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE ) )
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return false;
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if( !reportProgress( ii++, count, progressDelta ) )
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return false;
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if( isInvisibleText( item ) )
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return true;
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for( PCB_LAYER_ID layer : silkLayers.Seq() )
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{
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if( !item->IsOnLayer( layer ) )
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continue;
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PCB_LAYER_ID maskLayer = layer == F_SilkS ? F_Mask : B_Mask;
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BOX2I itemBBox = item->GetBoundingBox();
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DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT,
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item, nullptr, maskLayer );
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int clearance = constraint.GetValue().Min();
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int actual;
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VECTOR2I pos;
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if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE || clearance < 0 )
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return true;
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std::shared_ptr<SHAPE> itemShape = item->GetEffectiveShape( layer );
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if( m_fullSolderMaskRTree->QueryColliding( itemBBox, itemShape.get(), maskLayer,
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clearance, &actual, &pos ) )
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{
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auto drce = DRC_ITEM::Create( DRCE_SILK_CLEARANCE );
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if( clearance > 0 )
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{
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wxString msg = formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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}
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drce->SetItems( item );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, pos, layer );
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}
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}
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return true;
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} );
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}
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bool isNullAperture( BOARD_ITEM* aItem )
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{
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if( aItem->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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if( pad->GetAttribute() == PAD_ATTRIB::NPTH
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&& ( pad->GetShape() == PAD_SHAPE::CIRCLE || pad->GetShape() == PAD_SHAPE::OVAL )
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&& pad->GetSize().x <= pad->GetDrillSize().x
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&& pad->GetSize().y <= pad->GetDrillSize().y )
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{
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return true;
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}
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}
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return false;
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}
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// Simple mask apertures aren't associated with copper items, so they only constitute a bridge
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// when they expose other copper items having at least two distinct nets. We use a map to record
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// the first net exposed by each mask aperture (on each copper layer).
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//
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// Note that this algorithm is also used for free pads.
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bool isMaskAperture( BOARD_ITEM* aItem )
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{
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if( aItem->Type() == PCB_PAD_T && static_cast<PAD*>( aItem )->IsFreePad() )
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return true;
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static const LSET saved( 2, F_Mask, B_Mask );
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LSET maskLayers = aItem->GetLayerSet() & saved;
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LSET otherLayers = aItem->GetLayerSet() & ~saved;
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return maskLayers.count() > 0 && otherLayers.count() == 0;
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}
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bool DRC_TEST_PROVIDER_SOLDER_MASK::checkMaskAperture( BOARD_ITEM* aMaskItem, BOARD_ITEM* aTestItem,
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PCB_LAYER_ID aTestLayer, int aTestNet,
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BOARD_ITEM** aCollidingItem )
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{
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if( aTestLayer == F_Mask && !aTestItem->IsOnLayer( F_Cu ) )
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return false;
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if( aTestLayer == B_Mask && !aTestItem->IsOnLayer( B_Cu ) )
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return false;
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FOOTPRINT* fp = aMaskItem->GetParentFootprint();
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if( fp && ( fp->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
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{
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// Mask apertures in footprints which allow soldermask bridges are ignored entirely.
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return false;
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}
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PTR_LAYER_CACHE_KEY key = { aMaskItem, aTestLayer };
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auto ii = m_maskApertureNetMap.find( key );
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if( ii == m_maskApertureNetMap.end() )
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{
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m_maskApertureNetMap[ key ] = { aTestItem, aTestNet };
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// First net; no bridge yet....
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return false;
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}
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if( ii->second.second == aTestNet && aTestNet > 0 )
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{
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// Same net; still no bridge...
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return false;
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}
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if( fp && ii->second.first->Type() == PCB_PAD_T && aTestItem->Type() == PCB_PAD_T )
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{
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PAD* alreadyEncounteredPad = static_cast<PAD*>( ii->second.first );
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PAD* thisPad = static_cast<PAD*>( aTestItem );
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if( alreadyEncounteredPad->SharesNetTieGroup( thisPad ) )
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return false;
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}
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*aCollidingItem = ii->second.first;
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return true;
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}
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bool DRC_TEST_PROVIDER_SOLDER_MASK::checkItemMask( BOARD_ITEM* aMaskItem, int aTestNet )
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{
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FOOTPRINT* fp = aMaskItem->GetParentFootprint();
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wxCHECK( fp, false );
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if( ( fp->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
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{
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// If we're allowing bridges then we're allowing bridges. Nothing to check.
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return false;
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}
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// Graphic items are used to implement net-ties between pads of a group within a net-tie
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// footprint. They must be allowed to intrude into their pad's mask aperture.
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if( aTestNet < 0 && aMaskItem->Type() == PCB_PAD_T && fp->IsNetTie() )
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{
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std::map<wxString, int> padNumberToGroupIdxMap = fp->MapPadNumbersToNetTieGroups();
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if( padNumberToGroupIdxMap[ static_cast<PAD*>( aMaskItem )->GetNumber() ] >= 0 )
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return false;
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}
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return true;
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}
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void DRC_TEST_PROVIDER_SOLDER_MASK::testItemAgainstItems( BOARD_ITEM* aItem, const BOX2I& aItemBBox,
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PCB_LAYER_ID aRefLayer,
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PCB_LAYER_ID aTargetLayer )
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{
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int itemNet = -1;
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if( aItem->IsConnected() )
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itemNet = static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode();
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BOARD_DESIGN_SETTINGS& bds = aItem->GetBoard()->GetDesignSettings();
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PAD* pad = dynamic_cast<PAD*>( aItem );
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PCB_VIA* via = dynamic_cast<PCB_VIA*>( aItem );
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std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aRefLayer );
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m_itemTree->QueryColliding( aItem, aRefLayer, aTargetLayer,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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FOOTPRINT* itemFP = aItem->GetParentFootprint();
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PAD* otherPad = dynamic_cast<PAD*>( other );
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int otherNet = -1;
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if( other->IsConnected() )
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otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
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if( otherNet > 0 && otherNet == itemNet )
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return false;
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if( isNullAperture( other ) )
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return false;
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if( itemFP && itemFP == other->GetParentFootprint() )
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{
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// Board-wide exclusion
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if( bds.m_AllowSoldermaskBridgesInFPs )
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return false;
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// Footprint-specific exclusion
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if( ( itemFP->GetAttributes() & FP_ALLOW_SOLDERMASK_BRIDGES ) > 0 )
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return false;
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}
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if( pad && otherPad && ( pad->SameLogicalPadAs( otherPad )
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|| pad->SharesNetTieGroup( otherPad ) ) )
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{
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return false;
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}
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BOARD_ITEM* a = aItem;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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auto it = m_checkedPairs.find( { a, b } );
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if( it != m_checkedPairs.end() && it->second.test( aTargetLayer ) )
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{
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return false;
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}
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else
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{
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m_checkedPairs[ { a, b } ].set( aTargetLayer );
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return true;
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}
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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PAD* otherPad = dynamic_cast<PAD*>( other );
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PCB_VIA* otherVia = dynamic_cast<PCB_VIA*>( other );
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auto otherShape = other->GetEffectiveShape( aTargetLayer );
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int otherNet = -1;
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if( other->IsConnected() )
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otherNet = static_cast<BOARD_CONNECTED_ITEM*>( other )->GetNetCode();
|
|
|
|
int actual;
|
|
VECTOR2I pos;
|
|
int clearance = 0;
|
|
|
|
if( aRefLayer == F_Mask || aRefLayer == B_Mask )
|
|
{
|
|
// Aperture-to-aperture must enforce web-min-width
|
|
clearance = m_webWidth;
|
|
}
|
|
else // ( aRefLayer == F_Cu || aRefLayer == B_Cu )
|
|
{
|
|
// Copper-to-aperture uses the solder-mask-to-copper-clearance
|
|
clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
|
|
}
|
|
|
|
if( pad )
|
|
clearance += pad->GetSolderMaskExpansion();
|
|
else if( via && !via->IsTented() )
|
|
clearance += via->GetSolderMaskExpansion();
|
|
|
|
if( otherPad )
|
|
clearance += otherPad->GetSolderMaskExpansion();
|
|
else if( otherVia && !otherVia->IsTented() )
|
|
clearance += otherVia->GetSolderMaskExpansion();
|
|
|
|
if( itemShape->Collide( otherShape.get(), clearance, &actual, &pos ) )
|
|
{
|
|
wxString msg;
|
|
BOARD_ITEM* colliding = nullptr;
|
|
|
|
if( aTargetLayer == F_Mask )
|
|
msg = _( "Front solder mask aperture bridges items with different nets" );
|
|
else
|
|
msg = _( "Rear solder mask aperture bridges items with different nets" );
|
|
|
|
// Simple mask apertures aren't associated with copper items, so they only
|
|
// constitute a bridge when they expose other copper items having at least
|
|
// two distinct nets.
|
|
if( isMaskAperture( aItem ) )
|
|
{
|
|
if( checkMaskAperture( aItem, other, aRefLayer, otherNet, &colliding ) )
|
|
{
|
|
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
|
|
|
|
drce->SetErrorMessage( msg );
|
|
drce->SetItems( aItem, colliding, other );
|
|
drce->SetViolatingRule( &m_bridgeRule );
|
|
reportViolation( drce, pos, aTargetLayer );
|
|
}
|
|
}
|
|
else if( isMaskAperture( other ) )
|
|
{
|
|
if( checkMaskAperture( other, aItem, aRefLayer, itemNet, &colliding ) )
|
|
{
|
|
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
|
|
|
|
drce->SetErrorMessage( msg );
|
|
drce->SetItems( other, colliding, aItem );
|
|
drce->SetViolatingRule( &m_bridgeRule );
|
|
reportViolation( drce, pos, aTargetLayer );
|
|
}
|
|
}
|
|
else if( checkItemMask( other, itemNet ) )
|
|
{
|
|
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
|
|
|
|
drce->SetErrorMessage( msg );
|
|
drce->SetItems( aItem, other );
|
|
drce->SetViolatingRule( &m_bridgeRule );
|
|
reportViolation( drce, pos, aTargetLayer );
|
|
}
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
},
|
|
m_largestClearance );
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskItemAgainstZones( BOARD_ITEM* aItem,
|
|
const BOX2I& aItemBBox,
|
|
PCB_LAYER_ID aMaskLayer,
|
|
PCB_LAYER_ID aTargetLayer )
|
|
{
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
if( !zone->GetLayerSet().test( aTargetLayer ) )
|
|
continue;
|
|
|
|
int zoneNet = zone->GetNetCode();
|
|
|
|
if( aItem->IsConnected() )
|
|
{
|
|
BOARD_CONNECTED_ITEM* connectedItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem );
|
|
|
|
if( zoneNet == connectedItem->GetNetCode() && zoneNet > 0 )
|
|
continue;
|
|
}
|
|
|
|
BOX2I inflatedBBox( aItemBBox );
|
|
int clearance = m_board->GetDesignSettings().m_SolderMaskToCopperClearance;
|
|
|
|
if( aItem->Type() == PCB_PAD_T )
|
|
clearance += static_cast<PAD*>( aItem )->GetSolderMaskExpansion();
|
|
else if( aItem->Type() == PCB_VIA_T )
|
|
clearance += static_cast<PCB_VIA*>( aItem )->GetSolderMaskExpansion();
|
|
|
|
inflatedBBox.Inflate( clearance );
|
|
|
|
if( !inflatedBBox.Intersects( zone->GetBoundingBox() ) )
|
|
continue;
|
|
|
|
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ zone ].get();
|
|
int actual;
|
|
VECTOR2I pos;
|
|
|
|
std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aMaskLayer );
|
|
|
|
if( zoneTree && zoneTree->QueryColliding( aItemBBox, itemShape.get(), aTargetLayer,
|
|
clearance, &actual, &pos ) )
|
|
{
|
|
wxString msg;
|
|
BOARD_ITEM* colliding = nullptr;
|
|
|
|
if( aMaskLayer == F_Mask )
|
|
msg = _( "Front solder mask aperture bridges items with different nets" );
|
|
else
|
|
msg = _( "Rear solder mask aperture bridges items with different nets" );
|
|
|
|
// Simple mask apertures aren't associated with copper items, so they only constitute
|
|
// a bridge when they expose other copper items having at least two distinct nets.
|
|
if( isMaskAperture( aItem ) && zoneNet >= 0 )
|
|
{
|
|
if( checkMaskAperture( aItem, zone, aTargetLayer, zoneNet, &colliding ) )
|
|
{
|
|
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
|
|
|
|
drce->SetErrorMessage( msg );
|
|
drce->SetItems( aItem, colliding, zone );
|
|
drce->SetViolatingRule( &m_bridgeRule );
|
|
reportViolation( drce, pos, aTargetLayer );
|
|
}
|
|
}
|
|
else
|
|
{
|
|
auto drce = DRC_ITEM::Create( DRCE_SOLDERMASK_BRIDGE );
|
|
|
|
drce->SetErrorMessage( msg );
|
|
drce->SetItems( aItem, zone );
|
|
drce->SetViolatingRule( &m_bridgeRule );
|
|
reportViolation( drce, pos, aTargetLayer );
|
|
}
|
|
}
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_SOLDER_MASK::testMaskBridges()
|
|
{
|
|
LSET copperAndMaskLayers = { 4, F_Mask, B_Mask, F_Cu, B_Cu };
|
|
|
|
const size_t progressDelta = 250;
|
|
int count = 0;
|
|
int ii = 0;
|
|
|
|
forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
|
|
[&]( BOARD_ITEM* item ) -> bool
|
|
{
|
|
++count;
|
|
return true;
|
|
} );
|
|
|
|
forEachGeometryItem( s_allBasicItemsButZones, copperAndMaskLayers,
|
|
[&]( BOARD_ITEM* item ) -> bool
|
|
{
|
|
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
|
|
return false;
|
|
|
|
if( !reportProgress( ii++, count, progressDelta ) )
|
|
return false;
|
|
|
|
BOX2I itemBBox = item->GetBoundingBox();
|
|
|
|
if( item->IsOnLayer( F_Mask ) && !isNullAperture( item ) )
|
|
{
|
|
// Test for aperture-to-aperture collisions
|
|
testItemAgainstItems( item, itemBBox, F_Mask, F_Mask );
|
|
|
|
// Test for aperture-to-zone collisions
|
|
testMaskItemAgainstZones( item, itemBBox, F_Mask, F_Cu );
|
|
}
|
|
else if( item->IsOnLayer( F_Cu ) )
|
|
{
|
|
// Test for copper-item-to-aperture collisions
|
|
testItemAgainstItems( item, itemBBox, F_Cu, F_Mask );
|
|
}
|
|
|
|
if( item->IsOnLayer( B_Mask ) && !isNullAperture( item ) )
|
|
{
|
|
// Test for aperture-to-aperture collisions
|
|
testItemAgainstItems( item, itemBBox, B_Mask, B_Mask );
|
|
|
|
// Test for aperture-to-zone collisions
|
|
testMaskItemAgainstZones( item, itemBBox, B_Mask, B_Cu );
|
|
}
|
|
else if( item->IsOnLayer( B_Cu ) )
|
|
{
|
|
// Test for copper-item-to-aperture collisions
|
|
testItemAgainstItems( item, itemBBox, B_Cu, B_Mask );
|
|
}
|
|
|
|
return true;
|
|
} );
|
|
}
|
|
|
|
|
|
bool DRC_TEST_PROVIDER_SOLDER_MASK::Run()
|
|
{
|
|
if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_CLEARANCE )
|
|
&& m_drcEngine->IsErrorLimitExceeded( DRCE_SOLDERMASK_BRIDGE ) )
|
|
{
|
|
reportAux( wxT( "Solder mask violations ignored. Tests not run." ) );
|
|
return true; // continue with other tests
|
|
}
|
|
|
|
m_board = m_drcEngine->GetBoard();
|
|
m_webWidth = m_board->GetDesignSettings().m_SolderMaskMinWidth;
|
|
m_maxError = m_board->GetDesignSettings().m_MaxError;
|
|
m_largestClearance = 0;
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
for( PAD* pad : footprint->Pads() )
|
|
m_largestClearance = std::max( m_largestClearance, pad->GetSolderMaskExpansion() );
|
|
}
|
|
|
|
// Order is important here: m_webWidth must be added in before m_largestCourtyardClearance is
|
|
// maxed with the various SILK_CLEARANCE_CONSTRAINTS.
|
|
m_largestClearance += m_largestClearance + m_webWidth;
|
|
|
|
DRC_CONSTRAINT worstClearanceConstraint;
|
|
|
|
if( m_drcEngine->QueryWorstConstraint( SILK_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
|
|
m_largestClearance = std::max( m_largestClearance, worstClearanceConstraint.m_Value.Min() );
|
|
|
|
reportAux( wxT( "Worst clearance : %d nm" ), m_largestClearance );
|
|
|
|
if( !reportPhase( _( "Building solder mask..." ) ) )
|
|
return false; // DRC cancelled
|
|
|
|
m_checkedPairs.clear();
|
|
m_maskApertureNetMap.clear();
|
|
|
|
buildRTrees();
|
|
|
|
if( !reportPhase( _( "Checking solder mask to silk clearance..." ) ) )
|
|
return false; // DRC cancelled
|
|
|
|
testSilkToMaskClearance();
|
|
|
|
if( !reportPhase( _( "Checking solder mask web integrity..." ) ) )
|
|
return false; // DRC cancelled
|
|
|
|
testMaskBridges();
|
|
|
|
reportRuleStatistics();
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
}
|
|
|
|
|
|
namespace detail
|
|
{
|
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_SOLDER_MASK> dummy;
|
|
}
|