291 lines
8.9 KiB
C++
291 lines
8.9 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019-2020 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef DRC_ENGINE_H
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#define DRC_ENGINE_H
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#include <board_commit.h>
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#include <class_board.h>
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#include <class_marker_pcb.h>
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#include <class_track.h>
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#include <geometry/seg.h>
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#include <geometry/shape_poly_set.h>
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#include <memory>
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#include <tools/pcb_tool_base.h>
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#include <vector>
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#include <drc_proto/drc_rule.h>
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class BOARD_DESIGN_SETTINGS;
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class PCB_EDIT_FRAME;
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class DIALOG_DRC;
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class BOARD_ITEM;
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class BOARD;
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class D_PAD;
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class ZONE_CONTAINER;
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class TRACK;
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class MARKER_PCB;
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class NETCLASS;
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class EDA_TEXT;
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class DRAWSEGMENT;
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class NETLIST;
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class PROGRESS_REPORTER;
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class REPORTER;
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namespace KIGFX
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{
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class WS_PROXY_VIEW_ITEM;
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};
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void drcPrintDebugMessage( int level, wxString msg, const char *function, int line );
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#define drc_dbg(level, fmt, ...) \
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drcPrintDebugMessage(level, wxString::Format( fmt, __VA_ARGS__ ), __FUNCTION__, __LINE__ );
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//#define drc_dbg(level, fmt, ...) \
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// wxLogTrace("DUPA", fmt, __VA_ARGS__);
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namespace test
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{
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class DRC_RULE_CONDITION;
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class DRC_ITEM;
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class DRC_RULE;
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class DRC_TEST_PROVIDER;
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class DRC_CONSTRAINT;
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enum DRC_CONSTRAINT_QUERY_T
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{
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DRCCQ_LARGEST_MINIMUM = 0
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// fixme: more to come I guess...
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};
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/// DRC error codes:
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enum PCB_DRC_CODE
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{
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DRCE_FIRST = 1,
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DRCE_UNCONNECTED_ITEMS = DRCE_FIRST, ///< items are unconnected
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DRCE_SHORTING_ITEMS, ///< items shorting two nets but not a net-tie
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DRCE_ALLOWED_ITEMS, ///< a disallowed item has been used
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DRCE_CLEARANCE, ///< items are too close together
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DRCE_TRACKS_CROSSING, ///< tracks are crossing
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DRCE_COPPER_EDGE_CLEARANCE, ///< a copper item is too close to the board edge
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DRCE_ZONES_INTERSECT, ///< copper area outlines intersect
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DRCE_ZONE_HAS_EMPTY_NET, ///< copper area has a net but no pads in nets, which is suspicious
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DRCE_DANGLING_VIA, ///< via which isn't connected to anything
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DRCE_DANGLING_TRACK, ///< track with at least one end not connected to anything
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DRCE_HOLE_CLEARANCE, ///< overlapping drilled holes break drill bits
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DRCE_TRACK_WIDTH, ///< Track width is too small or too large
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DRCE_TOO_SMALL_VIA, ///< Too small via size
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DRCE_ANNULUS, ///< Via size and drill leave annulus too small or too large
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DRCE_TOO_SMALL_DRILL, ///< Too small via or pad drill
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DRCE_VIA_HOLE_BIGGER, ///< via's hole is bigger than its diameter
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DRCE_PADSTACK, ///< something is wrong with a pad or via stackup
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DRCE_TOO_SMALL_MICROVIA, ///< Too small micro via size
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DRCE_TOO_SMALL_MICROVIA_DRILL, ///< Too small micro via drill
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DRCE_KEEPOUT, ///< A disallowed object is inside a keepout
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DRCE_OVERLAPPING_FOOTPRINTS, ///< footprint courtyards overlap
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DRCE_MISSING_COURTYARD, ///< footprint has no courtyard defined
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DRCE_MALFORMED_COURTYARD, ///< footprint has a courtyard but malformed
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///< (not convertible to a closed polygon with holes)
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DRCE_PTH_IN_COURTYARD,
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DRCE_NPTH_IN_COURTYARD,
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DRCE_DISABLED_LAYER_ITEM, ///< item on a disabled layer
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DRCE_INVALID_OUTLINE, ///< invalid board outline
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DRCE_MISSING_FOOTPRINT, ///< footprint not found for netlist item
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DRCE_DUPLICATE_FOOTPRINT, ///< more than one footprints found for netlist item
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DRCE_EXTRA_FOOTPRINT, ///< netlist item not found for footprint
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DRCE_UNRESOLVED_VARIABLE,
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DRCE_VIA_DIAMETER, ///< Via diameter checks (min/max)
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DRCE_LAST = DRCE_UNRESOLVED_VARIABLE
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};
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class DRC_REPORT
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{
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public:
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struct ENTRY
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{
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std::shared_ptr<DRC_ITEM> m_item;
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::MARKER_PCB* m_marker;
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};
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typedef std::vector<ENTRY> ENTRIES;
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DRC_REPORT() {};
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~DRC_REPORT();
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void AddItem( std::shared_ptr<DRC_ITEM> aItem, ::MARKER_PCB *aMarker = nullptr)
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{
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ENTRY ent;
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ent.m_item = aItem;
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ent.m_marker = aMarker;
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m_entries.push_back(ent);
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}
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const ENTRIES& GetReportEntries() const { return m_entries; };
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private:
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ENTRIES m_entries;
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};
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/**
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* Design Rule Checker object that performs all the DRC tests. The output of
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* the checking goes to the BOARD file in the form of two MARKER lists. Those
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* two lists are displayable in the drc dialog box. And they can optionally
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* be sent to a text file on disk.
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* This class is given access to the windows and the BOARD
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* that it needs via its constructor or public access functions.
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*/
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class DRC_ENGINE
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{
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public:
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DRC_ENGINE( BOARD* aBoard, BOARD_DESIGN_SETTINGS* aSettings );
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~DRC_ENGINE();
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void SetSchematicNetlist( NETLIST* aNetlist )
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{
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m_schematicNetlist = aNetlist;
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}
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NETLIST* GetSchematicNetlist() const
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{
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return m_schematicNetlist;
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}
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void SetWorksheet( KIGFX::WS_PROXY_VIEW_ITEM* aWorksheet )
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{
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m_worksheet = aWorksheet;
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}
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KIGFX::WS_PROXY_VIEW_ITEM* GetWorksheet() const
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{
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return m_worksheet;
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}
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void SetProgressReporter( PROGRESS_REPORTER* aProgRep )
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{
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m_progressReporter = aProgRep;
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}
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void SetLogReporter( REPORTER* aReporter )
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{
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m_reporter = aReporter;
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}
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bool LoadRules( wxFileName aPath );
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void RunTests();
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void SetErrorLimit( int aLimit );
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BOARD_DESIGN_SETTINGS* GetDesignSettings() const
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{
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return m_designSettings;
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}
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BOARD* GetBoard() const
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{
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return m_board;
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}
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const DRC_CONSTRAINT& EvalRulesForItems(
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DRC_CONSTRAINT_TYPE_T ruleID, BOARD_ITEM* a, BOARD_ITEM* b = nullptr, PCB_LAYER_ID aLayer = UNDEFINED_LAYER );
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std::vector<DRC_CONSTRAINT> QueryConstraintsById( test::DRC_CONSTRAINT_TYPE_T ruleID );
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bool HasCorrectRulesForId( test::DRC_CONSTRAINT_TYPE_T ruleID );
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EDA_UNITS UserUnits() const
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{
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return EDA_UNITS::MILLIMETRES;
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}
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bool CompileRules();
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void Report( std::shared_ptr<DRC_ITEM> aItem, ::MARKER_PCB *Marker );
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void ReportProgress( double aProgress );
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void ReportStage ( const wxString& aStageName, int index, int total );
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void ReportAux( const wxString& aStr );
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std::shared_ptr<DRC_REPORT> GetReport() const { return m_drcReport; }
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bool QueryWorstConstraint( DRC_CONSTRAINT_TYPE_T aRuleId, test::DRC_CONSTRAINT& aConstraint, DRC_CONSTRAINT_QUERY_T aQueryType );
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private:
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void addRule( test::DRC_RULE* rule )
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{
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m_rules.push_back(rule);
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}
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void freeCompiledRules();
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struct CONSTRAINT_WITH_CONDITIONS
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{
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std::vector<test::DRC_RULE_CONDITION*> conditions;
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test::DRC_RULE* parentRule;
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test::DRC_CONSTRAINT constraint;
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};
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struct CONSTRAINT_SET
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{
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std::vector<CONSTRAINT_WITH_CONDITIONS*> sortedConstraints;
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DRC_TEST_PROVIDER* provider;
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};
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typedef std::unordered_map<test::DRC_CONSTRAINT_TYPE_T, CONSTRAINT_SET*> CONSTRAINT_MAP;
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void inferLegacyRules();
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void loadTestProviders();
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test::DRC_RULE* createInferredRule( const wxString& name, std::set<BOARD_ITEM*> items, int priority );
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BOARD_DESIGN_SETTINGS* m_designSettings;
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BOARD* m_board;
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KIGFX::WS_PROXY_VIEW_ITEM* m_worksheet;
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NETLIST* m_schematicNetlist;
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std::shared_ptr<DRC_REPORT> m_drcReport;
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std::vector<DRC_RULE_CONDITION*> m_ruleConditions;
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std::vector<DRC_RULE*> m_rules;
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std::vector<DRC_TEST_PROVIDER*> m_testProviders;
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std::unordered_map<EDA_ITEM*, CONSTRAINT_SET*> m_implicitRules;
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CONSTRAINT_MAP m_constraintMap;
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REPORTER* m_reporter;
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PROGRESS_REPORTER* m_progressReporter;
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// condition -> rule -> provider
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};
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}; // namespace test
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#endif // DRC_H
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