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(title "TinyTapeout 4/5 Demo Board PRELIM")
(date "2023-11-22")
(rev "1.0.4")
(company "Psychogenic Technologies")
(comment 1 "See LICENSE.txt for details")
(comment 2 "Licensed under Apache 2.0")
(comment 3 "(C) 2023 Pat Deegan")
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(text "Extensive labelling, designed for TT4+ with new MUX, \nRP2040 on board, accessed via USB.\nProject clock from RP2040, external or manual, DIP\nswitches for inputs, 7-segment display (remappable with \njumpers) on outputs, full access to 8 in, out and \nbidirectionals via PMODs, all pins broken out in headers. \n\n\nPower via +5V USB, or 5V breakout pin. On-board \nregulation to 3v3 and 1v8. VDDIO is 3v3, including\non PMODs."
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(text "Misc PU/PD.\nProject reset is pulled-up via\nthe user switch, project clock\nPD via its own manual switch."
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(text "Pinout follows non-numerical ordering in \norder to support various standard \ncommunications methods between IC and \nprojects. \n\nIn yellow, possible mappings for SPI, I2C\nand UART, from RP2040 perspective. See \nin sheet for full mapping.\n"
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(text "Wurth 157112V12700\nVf typ. 2V max 2.6V\nIcont 20mA"
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(at 295.91 217.17 90)
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(text "I/O is available through standard PMODs or, with judicious \nplacement, as a single 100mil pin header\n"
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(text "Pull-down just to \ndeal with accidental\ncontention on ~{cs}."
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(text "Changed to smaller SOT-23 LDO for core supply. If using the \n2112, can still get up to 600mA which is more than we need\nand should be safe for external draw."
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(text "3.3V +/- 10%\n+/- 25ppm \n\nUsing 830208220401\nbut 831056293 (with\nhalf the stability)\nshould do as well."
(exclude_from_sim no)
(at 175.26 195.58 0)
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(text "Defaults to flash boot (HIGH)\nWhen active (LOW): USB device\n\nThis pulls on the RP2040 flash\nSS line. Purposefully *not* \ndebounced, as we have on the\norder of 10us for a stable \nstate on boot. So either\nhold down + power-up, or \nhave a stiff pull with no\nRC filter in the loop."
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(text "Multiplexed signals to increase I/O at low cost.\nHK CS low gives access to both\n * HK SPI and\n * TT MUX control\nHK CS high provides access to out port (read \nfrom proj, so inputs here). We limit this to\nout* to avoid the need to maintain state while\nCS low. The recipe is RP2040 GPIO1:\n * LOW -> management (HK SPI/TT MUX)\n * HIGH -> interact with TT I/O"
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(text "PMOD host (female) headers,\nusing digilent's numbering."
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(text "The caravel flash is here as a DNP, just in case we want/need it. \nTT won't normally be using the caravel MCU, but it will still be present\nand will try to access this flash. Thus, we populate the pull-ups\nregardless of flash stuff status, and have some stable values on\nthe lines at all times."
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(text "E.g. if you wanted an SPI controlled\nperiphas part of your TT project, you \ncould configure it such that it uses:\nin[0] as select/~{cs}\nin[1] for clocking\nin[2] for tx/mosi\nand \nout[3] for rx/miso"
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(text "SoC ~{RST} is pulled-up but rising along \nwith power supply glitches the \nCPU.\nRef design uses \nMCP1319MT supervisor \nto handle and add a \ndebounced switch.\nA cap does the trick, \nTP1 available for all your \nexternal reset needs."
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(text "PMOD, specialized versions. These PMODs offer an array of options while attempting to keep to\nstandard digilent pinouts. With \"SPI Slave\", the pmod controls the bus and the project responds.\nOn \"SPI Master\", the pmod is a peripheral device to the project. The bidir/uart header is flexible.\n"
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(text "Manual clocking needs to be \ndebounced, but we don't want \na big RC filter on the project\nclock as the RP2040 may want \nfast edges.\nGetting the signal from between\nR12/R41 makes both of these \npossible simultaneously."
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(text "For reference, digilent standard pinouts"
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(text "NOTE: this is the *caravel* clock. For \nprojects, either feed in via project_clk\nheader pin, clock manually using SW1, or\nuse the RP2040 RP_proj_clk pin."
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(text "Jumpers allow manual disable/reassign \nof output -> segments (see footprint)"
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