547 lines
21 KiB
C++
547 lines
21 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
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* Copyright (C) 2007 Dick Hollenbeck, dick@softplc.com
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* Copyright (C) 2019 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <fctsys.h>
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#include <trigo.h>
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#include <drc/drc.h>
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#include <class_board.h>
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#include <class_track.h>
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#include <class_drawsegment.h>
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#include <class_marker_pcb.h>
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#include <geometry/polygon_test_point_inside.h>
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#include <geometry/shape_rect.h>
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#include <geometry/shape_segment.h>
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void DRC::doSingleViaDRC( BOARD_COMMIT& aCommit, VIA* aRefVia )
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{
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BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
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// test if the via size is smaller than minimum
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if( aRefVia->GetViaType() == VIATYPE::MICROVIA )
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{
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if( aRefVia->GetWidth() < bds.m_MicroViasMinSize )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
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m_msg.Printf( drcItem->GetErrorText() + _( " (board minimum %s; actual %s)" ),
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MessageTextFromValue( userUnits(), bds.m_MicroViasMinSize, true ),
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MessageTextFromValue( userUnits(), aRefVia->GetWidth(), true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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}
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else
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{
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if( aRefVia->GetWidth() < bds.m_ViasMinSize )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
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m_msg.Printf( drcItem->GetErrorText() + _( " (board minimum %s; actual %s)" ),
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MessageTextFromValue( userUnits(), bds.m_ViasMinSize, true ),
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MessageTextFromValue( userUnits(), aRefVia->GetWidth(), true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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}
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// test if via's hole is bigger than its diameter
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// This test is necessary since the via hole size and width can be modified
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// and a default via hole can be bigger than some vias sizes
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if( aRefVia->GetDrillValue() > aRefVia->GetWidth() )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_VIA_HOLE_BIGGER );
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m_msg.Printf( drcItem->GetErrorText() + _( " (diameter %s; drill %s)" ),
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MessageTextFromValue( userUnits(), aRefVia->GetWidth(), true ),
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MessageTextFromValue( userUnits(), aRefVia->GetDrillValue(), true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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// test if the type of via is allowed due to design rules
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if( aRefVia->GetViaType() == VIATYPE::MICROVIA && !bds.m_MicroViasAllowed )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
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m_msg.Printf( _( "Microvia not allowed (board design rule constraints)" ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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// test if the type of via is allowed due to design rules
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if( aRefVia->GetViaType() == VIATYPE::BLIND_BURIED && !bds.m_BlindBuriedViaAllowed )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ALLOWED_ITEMS );
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m_msg.Printf( _( "Blind/buried via not allowed (board design rule constraints)" ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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// For microvias: test if they are blind vias and only between 2 layers
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// because they are used for very small drill size and are drill by laser
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// and **only one layer** can be drilled
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if( aRefVia->GetViaType() == VIATYPE::MICROVIA )
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{
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PCB_LAYER_ID layer1, layer2;
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bool err = true;
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aRefVia->LayerPair( &layer1, &layer2 );
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if( layer1 > layer2 )
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std::swap( layer1, layer2 );
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if( layer2 == B_Cu && layer1 == bds.GetCopperLayerCount() - 2 )
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err = false;
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else if( layer1 == F_Cu && layer2 == In1_Cu )
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err = false;
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else if ( layer1 == layer2 - 1 )
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err = false;
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if( err )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_PADSTACK );
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m_msg.Printf( _( "Microvia through too many layers (%s and %s not adjacent)" ),
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m_pcb->GetLayerName( layer1 ),
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m_pcb->GetLayerName( layer2 ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefVia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefVia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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}
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}
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void DRC::doSingleTrackDRC( BOARD_COMMIT& aCommit, TRACK* aRefSeg )
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{
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SHAPE_SEGMENT refSeg( aRefSeg->GetStart(), aRefSeg->GetEnd(), aRefSeg->GetWidth() );
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EDA_RECT refSegBB = aRefSeg->GetBoundingBox();
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int refSegWidth = aRefSeg->GetWidth();
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int minWidth, maxWidth;
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aRefSeg->GetWidthConstraints( &minWidth, &maxWidth, &m_clearanceSource );
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int errorCode = 0;
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int constraintWidth;
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if( refSegWidth < minWidth )
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{
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errorCode = DRCE_TRACK_WIDTH;
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constraintWidth = minWidth;
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}
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else if( refSegWidth > maxWidth )
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{
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errorCode = DRCE_TRACK_WIDTH;
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constraintWidth = maxWidth;
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}
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if( errorCode )
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{
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wxPoint refsegMiddle = ( aRefSeg->GetStart() + aRefSeg->GetEnd() ) / 2;
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( errorCode );
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m_msg.Printf( drcItem->GetErrorText() + _( " (%s %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), constraintWidth, true ),
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MessageTextFromValue( userUnits(), refSegWidth, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefSeg );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, refsegMiddle );
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addMarkerToPcb( aCommit, marker );
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}
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}
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void DRC::doTrackDrc( BOARD_COMMIT& aCommit, TRACK* aRefSeg, TRACKS::iterator aStartIt,
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TRACKS::iterator aEndIt, bool aTestZones, PCB_LAYER_ID aLayer )
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{
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BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
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SHAPE_SEGMENT refSeg( aRefSeg->GetStart(), aRefSeg->GetEnd(), aRefSeg->GetWidth() );
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EDA_RECT refSegBB = aRefSeg->GetBoundingBox();
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SEG testSeg( aRefSeg->GetStart(), aRefSeg->GetEnd() );
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int halfWidth = ( aRefSeg->GetWidth() + 1 ) / 2;
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/******************************************/
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/* Phase 0 : via DRC tests : */
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/******************************************/
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if( aRefSeg->Type() == PCB_VIA_T )
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{
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VIA* refvia = static_cast<VIA*>( aRefSeg );
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int viaAnnulus = ( refvia->GetWidth() - refvia->GetDrill() ) / 2;
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int minAnnulus = refvia->GetMinAnnulus( aLayer, &m_clearanceSource );
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if( !refvia->IsPadOnLayer( aLayer ) )
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{
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halfWidth = ( refvia->GetDrillValue() + 1 ) / 2;
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refSegBB = EDA_RECT( refvia->GetStart(),
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wxSize( refvia->GetDrillValue(), refvia->GetDrillValue() ) );
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}
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// test if the via size is smaller than minimum
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if( refvia->GetViaType() == VIATYPE::MICROVIA )
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{
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if( viaAnnulus < minAnnulus )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
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m_msg.Printf( _( "Via annulus too small (%s %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), minAnnulus, true ),
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MessageTextFromValue( userUnits(), viaAnnulus, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( refvia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, refvia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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}
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else
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{
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if( bds.m_ViasMinAnnulus > minAnnulus )
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{
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minAnnulus = bds.m_ViasMinAnnulus;
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m_clearanceSource = _( "board minimum" );
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}
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if( viaAnnulus < minAnnulus )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
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m_msg.Printf( _( "Via annulus too small (%s %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), minAnnulus, true ),
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MessageTextFromValue( userUnits(), viaAnnulus, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( refvia );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, refvia->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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}
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}
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}
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/******************************************/
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/* Phase 1 : test DRC track to pads : */
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/******************************************/
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// Compute the min distance to pads
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for( MODULE* mod : m_pcb->Modules() )
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{
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// Don't preflight at the module level. Getting a module's bounding box goes
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// through all its pads anyway (so it's no faster), and also all its drawings
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// (so it's in fact slower).
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for( D_PAD* pad : mod->Pads() )
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{
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// Preflight based on bounding boxes.
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EDA_RECT inflatedBB = refSegBB;
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inflatedBB.Inflate( pad->GetBoundingRadius() + m_largestClearance );
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if( !inflatedBB.Contains( pad->GetPosition() ) )
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continue;
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if( !( pad->IsOnLayer( aLayer ) ) )
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continue;
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// No need to check pads with the same net as the refSeg.
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if( pad->GetNetCode() && aRefSeg->GetNetCode() == pad->GetNetCode() )
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continue;
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if( pad->GetDrillSize().x > 0 )
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{
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const SHAPE_SEGMENT* slot = pad->GetEffectiveHoleShape();
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const DRC_CONSTRAINT* constraint = GetConstraint( aRefSeg, pad,
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DRC_CONSTRAINT_TYPE_CLEARANCE,
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aLayer, &m_clearanceSource );
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int minClearance;
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int actual;
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if( constraint )
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{
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m_clearanceSource = wxString::Format( _( "'%s' rule" ), m_clearanceSource );
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minClearance = constraint->m_Value.Min();
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}
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else
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{
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minClearance = aRefSeg->GetClearance( aLayer, nullptr, &m_clearanceSource );
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}
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if( pad->GetAttribute() == PAD_ATTRIB_STANDARD )
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minClearance += bds.GetHolePlatingThickness();
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if( slot->Collide( &refSeg, minClearance + bds.GetDRCEpsilon(), &actual ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), actual, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefSeg, pad );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, pad->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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if( !m_reportAllTrackErrors )
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return;
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}
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}
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/// Skip checking pad copper when it has been removed
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if( !pad->IsPadOnLayer( aLayer ) )
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continue;
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int minClearance = aRefSeg->GetClearance( aLayer, pad, &m_clearanceSource );
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int actual;
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if( pad->Collide( &refSeg, minClearance - bds.GetDRCEpsilon(), &actual ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), actual, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefSeg, pad );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, pad->GetPosition() );
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addMarkerToPcb( aCommit, marker );
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if( !m_reportAllTrackErrors )
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return;
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}
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}
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}
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/***********************************************/
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/* Phase 2: test DRC with other track segments */
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/***********************************************/
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// Test the reference segment with other track segments
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for( auto it = aStartIt; it != aEndIt; it++ )
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{
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TRACK* track = *it;
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// No problem if segments have the same net code:
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if( aRefSeg->GetNetCode() == track->GetNetCode() )
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continue;
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if( !track->GetLayerSet().test( aLayer ) )
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continue;
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// Preflight based on worst-case inflated bounding boxes:
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EDA_RECT trackBB = track->GetBoundingBox();
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trackBB.Inflate( m_largestClearance );
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if( !trackBB.Intersects( refSegBB ) )
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continue;
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int minClearance = aRefSeg->GetClearance( aLayer, track, &m_clearanceSource );
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int actual;
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SHAPE_SEGMENT trackSeg( track->GetStart(), track->GetEnd(), track->GetWidth() );
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/// Check to see if the via has a pad on this layer
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if( track->Type() == PCB_VIA_T )
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{
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VIA* via = static_cast<VIA*>( track );
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if( !via->IsPadOnLayer( aLayer ) )
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trackSeg.SetWidth( via->GetDrillValue() );
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}
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// Check two tracks crossing first as it reports a DRCE without distances
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if( OPT_VECTOR2I intersection = refSeg.GetSeg().Intersect( trackSeg.GetSeg() ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACKS_CROSSING );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefSeg, track );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, (wxPoint) intersection.get() );
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addMarkerToPcb( aCommit, marker );
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if( !m_reportAllTrackErrors )
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return;
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}
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else if( refSeg.Collide( &trackSeg, minClearance - bds.GetDRCEpsilon(), &actual ) )
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{
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wxPoint pos = GetLocation( aRefSeg, trackSeg.GetSeg() );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
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m_clearanceSource,
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MessageTextFromValue( userUnits(), minClearance, true ),
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MessageTextFromValue( userUnits(), actual, true ) );
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drcItem->SetErrorMessage( m_msg );
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drcItem->SetItems( aRefSeg, track );
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MARKER_PCB* marker = new MARKER_PCB( drcItem, pos );
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addMarkerToPcb( aCommit, marker );
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if( !m_reportAllTrackErrors )
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return;
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}
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}
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/***************************************/
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/* Phase 3: test DRC with copper zones */
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/***************************************/
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// Can be *very* time consumming.
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if( aTestZones )
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{
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for( ZONE_CONTAINER* zone : m_pcb->Zones() )
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{
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if( !zone->GetLayerSet().test( aLayer ) || zone->GetIsKeepout() )
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continue;
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if( zone->GetNetCode() && zone->GetNetCode() == aRefSeg->GetNetCode() )
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continue;
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if( zone->GetFilledPolysList( aLayer ).IsEmpty() )
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continue;
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int minClearance = aRefSeg->GetClearance( aLayer, zone, &m_clearanceSource );
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int allowedDist = minClearance + halfWidth - bds.GetDRCEpsilon();
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int actual;
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if( zone->GetFilledPolysList( aLayer ).Collide( testSeg, allowedDist, &actual ) )
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{
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actual = std::max( 0, actual - halfWidth );
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
|
m_clearanceSource,
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
drcItem->SetItems( aRefSeg, zone );
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, GetLocation( aLayer, aRefSeg, zone ) );
|
|
addMarkerToPcb( aCommit, marker );
|
|
}
|
|
}
|
|
}
|
|
|
|
/***********************************************/
|
|
/* Phase 4: test DRC with to board edge */
|
|
/***********************************************/
|
|
if( m_board_outline_valid )
|
|
{
|
|
int minClearance = bds.m_CopperEdgeClearance;
|
|
m_clearanceSource = _( "board edge" );
|
|
|
|
static DRAWSEGMENT dummyEdge;
|
|
dummyEdge.SetParent( m_pcb );
|
|
dummyEdge.SetLayer( Edge_Cuts );
|
|
|
|
aRefSeg->GetRuleClearance( &dummyEdge, aLayer, &minClearance, &m_clearanceSource );
|
|
|
|
int center2centerAllowed = minClearance + halfWidth - bds.GetDRCEpsilon();
|
|
|
|
for( auto it = m_board_outlines.IterateSegmentsWithHoles(); it; it++ )
|
|
{
|
|
SEG::ecoord center2center_squared = testSeg.SquaredDistance( *it );
|
|
|
|
if( center2center_squared < SEG::Square( center2centerAllowed ) )
|
|
{
|
|
VECTOR2I pt = testSeg.NearestPoint( *it );
|
|
|
|
KICAD_T types[] = { PCB_LINE_T, EOT };
|
|
DRAWSEGMENT* edge = nullptr;
|
|
INSPECTOR_FUNC inspector =
|
|
[&] ( EDA_ITEM* item, void* testData )
|
|
{
|
|
DRAWSEGMENT* test_edge = dynamic_cast<DRAWSEGMENT*>( item );
|
|
|
|
if( !test_edge || test_edge->GetLayer() != Edge_Cuts )
|
|
return SEARCH_RESULT::CONTINUE;
|
|
|
|
if( test_edge->HitTest( (wxPoint) pt, minClearance + halfWidth ) )
|
|
{
|
|
edge = test_edge;
|
|
return SEARCH_RESULT::QUIT;
|
|
}
|
|
|
|
return SEARCH_RESULT::CONTINUE;
|
|
};
|
|
|
|
// Best-efforts search for edge segment
|
|
BOARD::IterateForward<BOARD_ITEM*>( m_pcb->Drawings(), inspector, nullptr, types );
|
|
|
|
int actual = std::max( 0.0, sqrt( center2center_squared ) - halfWidth );
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_COPPER_EDGE_CLEARANCE );
|
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
|
m_clearanceSource,
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
drcItem->SetItems( aRefSeg, edge );
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, (wxPoint) pt );
|
|
addMarkerToPcb( aCommit, marker );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|