324 lines
8.2 KiB
C++
324 lines
8.2 KiB
C++
/**********************************************************************/
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/* fonctions membres des classes utilisees dans pcbnew (voir pcbstruct.h */
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/* sauf routines relatives aux pistes (voir class_track.cpp) */
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/**********************************************************************/
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#include "fctsys.h"
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#include "wxstruct.h"
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#include "gr_basic.h"
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#include "common.h"
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#include "pcbnew.h"
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#ifdef CVPCB
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#include "cvpcb.h"
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#endif
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#include "protos.h"
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/**************************************************************/
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void EDA_BaseStruct::Place(WinEDA_DrawFrame * frame, wxDC * DC)
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/**************************************************************/
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/* fonction virtuelle de placement: non utilisee en pcbnew (utilisee eeschema)
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---- A mieux utiliser (TODO...)
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*/
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{
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}
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/**********************/
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/* Classe EDGE_ZONE */
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/**********************/
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/* Classe EDGE_ZONE: constructeur */
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EDGE_ZONE::EDGE_ZONE(EDA_BaseStruct * parent):
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DRAWSEGMENT( parent, TYPEEDGEZONE)
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{
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}
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/* Effacement memoire de la structure */
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EDGE_ZONE:: ~EDGE_ZONE(void)
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{
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}
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/**********************/
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/* Classe DRAWSEGMENT */
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/**********************/
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/* Classe DRAWSEGMENT: constructeur */
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DRAWSEGMENT::DRAWSEGMENT(EDA_BaseStruct * StructFather, DrawStructureType idtype):
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EDA_BaseLineStruct( StructFather, idtype)
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{
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m_Flags = m_Shape = m_Type = m_Angle = 0;
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}
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/* Effacement memoire de la structure */
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DRAWSEGMENT:: ~DRAWSEGMENT(void)
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{
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}
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void DRAWSEGMENT::UnLink( void )
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{
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/* Modification du chainage arriere */
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if( Pback )
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{
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if( Pback->m_StructType != TYPEPCB)
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{
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Pback->Pnext = Pnext;
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}
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else /* Le chainage arriere pointe sur la structure "Pere" */
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{
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((BOARD*)Pback)->m_Drawings = Pnext;
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}
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}
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/* Modification du chainage avant */
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if( Pnext) Pnext->Pback = Pback;
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Pnext = Pback = NULL;
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}
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/*******************************************/
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void DRAWSEGMENT::Copy(DRAWSEGMENT * source)
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/*******************************************/
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{
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m_Type = source->m_Type;
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m_Layer = source->m_Layer;
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m_Width = source->m_Width;
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m_Start = source->m_Start;
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m_End = source->m_End;
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m_Shape = source->m_Shape;
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m_Angle = source->m_Angle;
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m_TimeStamp = source->m_TimeStamp;
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}
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/********************************************************/
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bool DRAWSEGMENT::WriteDrawSegmentDescr(FILE * File)
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/********************************************************/
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{
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if( GetState(DELETED) ) return FALSE;
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fprintf( File, "$DRAWSEGMENT\n");
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fprintf( File,"Po %d %d %d %d %d %d\n",
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m_Shape,
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m_Start.x, m_Start.y,
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m_End.x, m_End.y, m_Width );
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fprintf( File,"De %d %d %d %lX %X\n",
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m_Layer, m_Type, m_Angle,
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m_TimeStamp, ReturnStatus());
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fprintf( File, "$EndDRAWSEGMENT\n");
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return TRUE;
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}
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/******************************************************************/
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bool DRAWSEGMENT::ReadDrawSegmentDescr(FILE * File, int * LineNum)
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/******************************************************************/
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/* Lecture de la description de 1 segment type Drawing PCB
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*/
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{
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char Line[2048];
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while( GetLine(File, Line, LineNum ) != NULL )
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{
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if(strnicmp(Line,"$End",4 ) == 0 ) return TRUE; /* fin de liste */
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if(Line[0] == 'P')
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{
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sscanf( Line+2," %d %d %d %d %d %d",
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&m_Shape, &m_Start.x, &m_Start.y,
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&m_End.x, &m_End.y, &m_Width );
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if ( m_Width < 0 ) m_Width = 0;
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}
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if(Line[0] == 'D')
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{
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int status;
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sscanf( Line+2," %d %d %d %lX %X",
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&m_Layer, &m_Type, &m_Angle,
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&m_TimeStamp, &status);
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if ( m_Layer < FIRST_NO_COPPER_LAYER )
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m_Layer = FIRST_NO_COPPER_LAYER;
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if ( m_Layer > LAST_NO_COPPER_LAYER )
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m_Layer = LAST_NO_COPPER_LAYER;
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SetState(status, ON);
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}
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}
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return FALSE;
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}
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/*******************/
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/* Classe MARQUEUR */
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/*******************/
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MARQUEUR::MARQUEUR(EDA_BaseStruct * StructFather):
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EDA_BaseStruct( StructFather, TYPEMARQUEUR)
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{
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m_Bitmap = NULL;
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m_Type = 0;
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m_Color = RED;
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}
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/* Effacement memoire de la structure */
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MARQUEUR:: ~MARQUEUR(void)
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{
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}
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/* supprime du chainage la structure Struct
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les structures arrieres et avant sont chainees directement
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*/
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void MARQUEUR::UnLink( void )
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{
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/* Modification du chainage arriere */
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if( Pback )
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{
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if( Pback->m_StructType != TYPEPCB)
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{
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Pback->Pnext = Pnext;
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}
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else /* Le chainage arriere pointe sur la structure "Pere" */
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{
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((BOARD*)Pback)->m_Drawings = Pnext;
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}
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}
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/* Modification du chainage avant */
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if( Pnext) Pnext->Pback = Pback;
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Pnext = Pback = NULL;
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}
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/**************************************************/
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/* Class SCREEN: classe de gestion d'un affichage */
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/***************************************************/
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/* Constructeur de SCREEN */
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PCB_SCREEN::PCB_SCREEN(int idscreen): BASE_SCREEN(TYPESCREEN)
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{
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int zoom_list[] = {1,2,4,8,16,32,64,128,256,512,1024,2048,0};
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m_Type = idscreen;
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SetGridList(g_GridList);
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SetZoomList(zoom_list);
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Init();
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}
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/***************************/
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PCB_SCREEN::~PCB_SCREEN(void)
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/***************************/
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{
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}
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/*************************/
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void PCB_SCREEN::Init(void)
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/*************************/
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{
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InitDatas();
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m_Active_Layer = CUIVRE_N; /* ref couche active 0.. 31 */
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m_Route_Layer_TOP = CMP_N; /* ref couches par defaut pour vias (Cu.. Cmp) */
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m_Route_Layer_BOTTOM = CUIVRE_N;
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m_Zoom = 128; /* valeur */
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m_Grid = wxSize(500,500); /* pas de la grille en 1/10000 "*/
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}
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/*************************/
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/* class DISPLAY_OPTIONS */
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/*************************/
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/*
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Options diverses d'affichage <20> l'<27>cran:
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*/
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DISPLAY_OPTIONS::DISPLAY_OPTIONS(void)
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{
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DisplayPadFill = TRUE;
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DisplayPadNum = TRUE;
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DisplayPadNoConn = TRUE;
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DisplayPadIsol = TRUE;
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DisplayModEdge = TRUE;
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DisplayModText = TRUE;
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DisplayPcbTrackFill = TRUE; /* FALSE = sketch , TRUE = rempli */
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DisplayTrackIsol = FALSE;
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m_DisplayViaMode = VIA_HOLE_NOT_SHOW;
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DisplayPolarCood = TRUE;
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DisplayZones = TRUE;
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Show_Modules_Cmp = TRUE;
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Show_Modules_Cu = TRUE;
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DisplayDrawItems = TRUE;
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ContrastModeDisplay = FALSE;
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}
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/*****************************************************/
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EDA_BoardDesignSettings::EDA_BoardDesignSettings(void)
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/*****************************************************/
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// Default values for designing boards
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{
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int ii;
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int default_layer_color[32]= {
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GREEN, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, RED,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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MAGENTA, CYAN,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY };
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m_CopperLayerCount = 2; // Default design is a double sided board
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m_ViaDrill = 250; // via drill (for the entire board)
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m_CurrentViaSize = 450; // Current via size
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m_CurrentViaType = VIA_NORMALE; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/
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m_CurrentTrackWidth = 170; // current track width
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for ( ii = 0; ii < HIST0RY_NUMBER; ii ++ )
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{
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m_TrackWidhtHistory[ii] = 0; // Last HIST0RY_NUMBER used track widths
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m_ViaSizeHistory[ii] = 0; // Last HIST0RY_NUMBER used via sizes
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}
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m_DrawSegmentWidth = 100; // current graphic line width (not EDGE layer)
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m_EdgeSegmentWidth = 100; // current graphic line width (EDGE layer only)
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m_PcbTextWidth = 100; // current Pcb (not module) Text width
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m_PcbTextSize = wxSize(500,500); // current Pcb (not module) Text size
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m_TrackClearence = 100; // track to track and track to pads clearance
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m_ZoneClearence = 150; // zone to track and zone to pads clearance
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m_MaskMargin = 150; // Solder mask margin
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/* Color options for screen display of the Printed Board: */
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m_PcbGridColor = DARKGRAY; // Grid color
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for ( ii = 0; ii < 32; ii ++ )
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m_LayerColor[ii] = default_layer_color[ii]; // Layer colors (tracks and graphic items)
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m_ViaColor[VIA_BORGNE] = CYAN;
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m_ViaColor[VIA_ENTERREE] = BROWN;
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m_ViaColor[VIA_NORMALE] = WHITE;
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m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer
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m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer
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m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed)
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m_AnchorColor = BLUE; // Anchor color for modules and texts
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m_PadCUColor = GREEN; // Pad color for the COMPONENT side of the pad
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m_PadCMPColor = RED; // Pad color for the COPPER side of the pad
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m_RatsnestColor = WHITE; // Ratsnest color
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}
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