541 lines
18 KiB
C++
541 lines
18 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2007-2013 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 2007-2022 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/* This source is a complement to specctra.cpp and implements the import of
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a specctra session file (*.ses), and import of a specctra design file
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(*.dsn) file. The specification for the grammar of the specctra dsn file
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used to develop this code is given here:
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http://tech.groups.yahoo.com/group/kicad-users/files/ then file "specctra.pdf"
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Also see the comments at the top of the specctra.cpp file itself.
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*/
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#include <confirm.h> // DisplayError()
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#include <gestfich.h> // EDA_FileSelector()
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#include <pcb_edit_frame.h>
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#include <locale_io.h>
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#include <macros.h>
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#include <board.h>
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#include <board_design_settings.h>
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#include <footprint.h>
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#include <pcb_track.h>
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#include <connectivity/connectivity_data.h>
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#include <view/view.h>
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#include "specctra.h"
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#include <math/util.h> // for KiROUND
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#include <pcbnew_settings.h>
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using namespace DSN;
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bool PCB_EDIT_FRAME::ImportSpecctraSession( const wxString& fullFileName )
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{
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// To avoid issues with undo/redo lists (dangling pointers) clear the lists
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// todo: use undo/redo feature
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ClearUndoRedoList();
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// Remove existing tracks from view. They will be readded later after loading new tracks.
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if( GetCanvas() ) // clear view:
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{
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for( PCB_TRACK* track : GetBoard()->Tracks() )
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GetCanvas()->GetView()->Remove( track );
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}
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SPECCTRA_DB db;
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LOCALE_IO toggle;
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try
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{
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db.LoadSESSION( fullFileName );
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db.FromSESSION( GetBoard() );
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}
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catch( const IO_ERROR& ioe )
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{
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wxString msg = _( "Board may be corrupted, do not save it.\n Fix problem and try again" );
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wxString extra = ioe.What();
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DisplayErrorMessage( this, msg, extra);
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return false;
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}
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GetBoard()->GetConnectivity()->Clear();
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GetBoard()->BuildConnectivity();
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OnModify();
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if( GetCanvas() ) // Update view:
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{
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// Update footprint positions
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GetCanvas()->GetView()->RecacheAllItems();
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// add imported tracks (previous tracks are removed, therefore all are new)
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for( auto track : GetBoard()->Tracks() )
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GetCanvas()->GetView()->Add( track );
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}
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SetStatusText( wxString( _( "Session file imported and merged OK." ) ) );
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Refresh();
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return true;
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}
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namespace DSN {
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/**
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* Function scale
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* converts a session file distance to KiCad units of deci-mils.
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* @param distance The session file length to convert.
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* @param aResolution The session UNIT_RES which holds the engineering unit specifier
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* @return int - The KiCad length in internal unit
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*/
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static int scale( double distance, UNIT_RES* aResolution )
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{
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double resValue = aResolution->GetValue();
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double factor;
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switch( aResolution->GetEngUnits() )
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{
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default:
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case T_inch: factor = 25.4e6; break; // nanometers per inch
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case T_mil: factor = 25.4e3; break; // nanometers per mil
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case T_cm: factor = 1e7; break; // nanometers per cm
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case T_mm: factor = 1e6; break; // nanometers per mm
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case T_um: factor = 1e3; break; // nanometers per um
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}
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return KiROUND( factor * distance / resValue );
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}
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/**
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* Function mapPt
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* translates a point from the Specctra Session format coordinate system
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* to the KiCad coordinate system.
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* @param aPoint The session point to translate
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* @param aResolution - The amount to scale the point.
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* @return wxPoint - The KiCad coordinate system point.
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*/
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static wxPoint mapPt( const POINT& aPoint, UNIT_RES* aResolution )
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{
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wxPoint ret( scale( aPoint.x, aResolution ),
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-scale( aPoint.y, aResolution ) ); // negate y
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return ret;
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}
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PCB_TRACK* SPECCTRA_DB::makeTRACK( WIRE* wire, PATH* aPath, int aPointIndex, int aNetcode )
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{
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int layerNdx = findLayerName( aPath->layer_id );
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if( layerNdx == -1 )
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{
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THROW_IO_ERROR( wxString::Format( _( "Session file uses invalid layer id '%s'." ),
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FROM_UTF8( aPath->layer_id.c_str() ) ) );
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}
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PCB_TRACK* track = new PCB_TRACK( m_sessionBoard );
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track->SetStart( mapPt( aPath->points[aPointIndex+0], m_routeResolution ) );
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track->SetEnd( mapPt( aPath->points[aPointIndex+1], m_routeResolution ) );
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track->SetLayer( m_pcbLayer2kicad[layerNdx] );
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track->SetWidth( scale( aPath->aperture_width, m_routeResolution ) );
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track->SetNetCode( aNetcode );
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// a track can be locked.
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// However specctra as 4 types, none is exactly the same as our locked option
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// wire->wire_type = T_fix, T_route, T_normal or T_protect
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// fix and protect could be used as lock option
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// but protect is returned for all tracks having initially the route or protect property
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if( wire->wire_type == T_fix )
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track->SetLocked( true );
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return track;
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}
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PCB_VIA* SPECCTRA_DB::makeVIA( WIRE_VIA*aVia, PADSTACK* aPadstack, const POINT& aPoint, int aNetCode,
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int aViaDrillDefault )
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{
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PCB_VIA* via = 0;
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SHAPE* shape;
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int shapeCount = aPadstack->Length();
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int drill_diam_iu = -1;
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int copperLayerCount = m_sessionBoard->GetCopperLayerCount();
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// The drill diameter is encoded in the padstack name if Pcbnew did the DSN export.
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// It is after the colon and before the last '_'
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int drillStartNdx = aPadstack->padstack_id.find( ':' );
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if( drillStartNdx != -1 )
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{
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++drillStartNdx; // skip over the ':'
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int drillEndNdx = aPadstack->padstack_id.rfind( '_' );
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if( drillEndNdx != -1 )
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{
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std::string diam_txt( aPadstack->padstack_id,
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drillStartNdx, drillEndNdx-drillStartNdx );
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double drill_um = strtod( diam_txt.c_str(), 0 );
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drill_diam_iu = int( drill_um * ( pcbIUScale.IU_PER_MM / 1000.0 ) );
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if( drill_diam_iu == aViaDrillDefault )
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drill_diam_iu = UNDEFINED_DRILL_DIAMETER;
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}
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}
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if( shapeCount == 0 )
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{
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THROW_IO_ERROR( _( "Session via padstack has no shapes" ) );
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}
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else if( shapeCount == 1 )
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{
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shape = (SHAPE*) (*aPadstack)[0];
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DSN_T type = shape->shape->Type();
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if( type != T_circle )
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{
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THROW_IO_ERROR( wxString::Format( _( "Unsupported via shape: %s." ),
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GetTokenString( type ) ) );
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}
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CIRCLE* circle = (CIRCLE*) shape->shape;
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int viaDiam = scale( circle->diameter, m_routeResolution );
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via = new PCB_VIA( m_sessionBoard );
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via->SetPosition( mapPt( aPoint, m_routeResolution ) );
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via->SetDrill( drill_diam_iu );
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via->SetViaType( VIATYPE::THROUGH );
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via->SetWidth( viaDiam );
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via->SetLayerPair( F_Cu, B_Cu );
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}
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else if( shapeCount == copperLayerCount )
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{
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shape = (SHAPE*) (*aPadstack)[0];
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DSN_T type = shape->shape->Type();
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if( type != T_circle )
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{
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THROW_IO_ERROR( wxString::Format( _( "Unsupported via shape: %s" ),
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GetTokenString( type ) ) );
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}
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CIRCLE* circle = (CIRCLE*) shape->shape;
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int viaDiam = scale( circle->diameter, m_routeResolution );
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via = new PCB_VIA( m_sessionBoard );
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via->SetPosition( mapPt( aPoint, m_routeResolution ) );
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via->SetDrill( drill_diam_iu );
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via->SetViaType( VIATYPE::THROUGH );
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via->SetWidth( viaDiam );
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via->SetLayerPair( F_Cu, B_Cu );
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}
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else // VIA_MICROVIA or VIA_BLIND_BURIED
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{
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int topLayerNdx = -1; // session layer detectors
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int botLayerNdx = INT_MAX;
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int viaDiam = -1;
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for( int i=0; i<shapeCount; ++i )
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{
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shape = (SHAPE*) (*aPadstack)[i];
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DSN_T type = shape->shape->Type();
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if( type != T_circle )
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{
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THROW_IO_ERROR( wxString::Format( _( "Unsupported via shape: %s" ),
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GetTokenString( type ) ) );
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}
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CIRCLE* circle = (CIRCLE*) shape->shape;
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int layerNdx = findLayerName( circle->layer_id );
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if( layerNdx == -1 )
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{
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wxString layerName = FROM_UTF8( circle->layer_id.c_str() );
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THROW_IO_ERROR( wxString::Format( _( "Session file uses invalid layer id '%s'" ),
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layerName ) );
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}
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if( layerNdx > topLayerNdx )
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topLayerNdx = layerNdx;
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if( layerNdx < botLayerNdx )
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botLayerNdx = layerNdx;
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if( viaDiam == -1 )
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viaDiam = scale( circle->diameter, m_routeResolution );
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}
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via = new PCB_VIA( m_sessionBoard );
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via->SetPosition( mapPt( aPoint, m_routeResolution ) );
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via->SetDrill( drill_diam_iu );
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if( ( topLayerNdx == 0 && botLayerNdx == 1 )
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|| ( topLayerNdx == copperLayerCount-2 && botLayerNdx == copperLayerCount-1 ) )
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{
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via->SetViaType( VIATYPE::MICROVIA );
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}
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else
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{
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via->SetViaType( VIATYPE::BLIND_BURIED );
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}
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via->SetWidth( viaDiam );
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via->SetLayerPair( m_pcbLayer2kicad[ topLayerNdx ], m_pcbLayer2kicad[ botLayerNdx ] );
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}
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wxASSERT( via );
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via->SetNetCode( aNetCode );
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// a via can be locked.
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// However specctra as 4 types, none is exactly the same as our locked option
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// aVia->via_type = T_fix, T_route, T_normal or T_protect
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// fix and protect could be used as lock option
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// but protect is returned for all tracks having initially the route or protect property
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if( aVia->via_type == T_fix )
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via->SetLocked( true );
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return via;
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}
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// no UI code in this function, throw exception to report problems to the
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// UI handler: void PCB_EDIT_FRAME::ImportSpecctraSession( wxCommandEvent& event )
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void SPECCTRA_DB::FromSESSION( BOARD* aBoard )
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{
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m_sessionBoard = aBoard; // not owned here
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if( !m_session )
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THROW_IO_ERROR( _("Session file is missing the \"session\" section") );
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if( !m_session->route )
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THROW_IO_ERROR( _("Session file is missing the \"routes\" section") );
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if( !m_session->route->library )
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THROW_IO_ERROR( _("Session file is missing the \"library_out\" section") );
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// delete the old tracks and vias but save locked tracks/vias; they will be re-added later
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std::vector<PCB_TRACK*> locked;
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while( !aBoard->Tracks().empty() )
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{
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PCB_TRACK* track = aBoard->Tracks().back();
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aBoard->Tracks().pop_back();
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if( track->IsLocked() )
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locked.push_back( track );
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else
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delete track;
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}
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aBoard->DeleteMARKERs();
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buildLayerMaps( aBoard );
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// Add locked tracks: because they are exported as Fix tracks, they are not
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// in .ses file.
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for( PCB_TRACK* track: locked )
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aBoard->Add( track );
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if( m_session->placement )
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{
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// Walk the PLACEMENT object's COMPONENTs list, and for each PLACE within
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// each COMPONENT, reposition and re-orient each component and put on
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// correct side of the board.
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COMPONENTS& components = m_session->placement->components;
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for( COMPONENTS::iterator comp=components.begin(); comp!=components.end(); ++comp )
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{
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PLACES& places = comp->places;
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for( unsigned i=0; i<places.size(); ++i )
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{
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PLACE* place = &places[i]; // '&' even though places[] holds a pointer!
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wxString reference = FROM_UTF8( place->component_id.c_str() );
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FOOTPRINT* footprint = aBoard->FindFootprintByReference( reference );
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if( !footprint )
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{
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THROW_IO_ERROR( wxString::Format( _( "Reference '%s' not found." ),
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reference ) );
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}
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if( !place->hasVertex )
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continue;
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UNIT_RES* resolution = place->GetUnits();
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wxASSERT( resolution );
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wxPoint newPos = mapPt( place->vertex, resolution );
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footprint->SetPosition( newPos );
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if( place->side == T_front )
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{
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// convert from degrees to tenths of degrees used in KiCad.
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EDA_ANGLE orientation( place->rotation, DEGREES_T );
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if( footprint->GetLayer() != F_Cu )
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{
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// footprint is on copper layer (back)
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footprint->Flip( footprint->GetPosition(), false );
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}
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footprint->SetOrientation( orientation );
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}
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else if( place->side == T_back )
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{
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EDA_ANGLE orientation( place->rotation + 180.0, DEGREES_T );
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if( footprint->GetLayer() != B_Cu )
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{
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// footprint is on component layer (front)
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footprint->Flip( footprint->GetPosition(), false );
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}
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footprint->SetOrientation( orientation );
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}
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else
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{
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// as I write this, the PARSER *is* catching this, so we should never see below:
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wxFAIL_MSG( wxT("DSN::PARSER did not catch an illegal side := 'back|front'") );
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}
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}
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}
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}
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m_routeResolution = m_session->route->GetUnits();
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// Walk the NET_OUTs and create tracks and vias anew.
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NET_OUTS& net_outs = m_session->route->net_outs;
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for( NET_OUTS::iterator net = net_outs.begin(); net!=net_outs.end(); ++net )
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{
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int netoutCode = 0;
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// page 143 of spec says wire's net_id is optional
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if( net->net_id.size() )
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{
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wxString netName = FROM_UTF8( net->net_id.c_str() );
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NETINFO_ITEM* netinfo = aBoard->FindNet( netName );
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if( netinfo )
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netoutCode = netinfo->GetNetCode();
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}
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WIRES& wires = net->wires;
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for( unsigned i = 0; i<wires.size(); ++i )
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{
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WIRE* wire = &wires[i];
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DSN_T shape = wire->shape->Type();
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if( shape != T_path )
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{
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/*
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* shape == T_polygon is expected from freerouter if you have a zone on a non-
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* "power" type layer, i.e. a T_signal layer and the design does a round-trip
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* back in as session here. We kept our own zones in the BOARD, so ignore this
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* so called 'wire'.
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wxString netId = FROM_UTF8( wire->net_id.c_str() );
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THROW_IO_ERROR( wxString::Format( _( "Unsupported wire shape: '%s' for net: '%s'" ),
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DLEX::GetTokenString(shape).GetData(),
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netId.GetData() ) );
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*/
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}
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else
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{
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PATH* path = (PATH*) wire->shape;
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for( unsigned pt=0; pt < path->points.size()-1; ++pt )
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{
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PCB_TRACK* track = makeTRACK( wire, path, pt, netoutCode );
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aBoard->Add( track );
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}
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}
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}
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WIRE_VIAS& wire_vias = net->wire_vias;
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LIBRARY& library = *m_session->route->library;
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for( unsigned i=0; i<wire_vias.size(); ++i )
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{
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int netCode = 0;
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// page 144 of spec says wire_via's net_id is optional
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if( net->net_id.size() )
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{
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wxString netName = FROM_UTF8( net->net_id.c_str() );
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NETINFO_ITEM* netvia = aBoard->FindNet( netName );
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if( netvia )
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netCode = netvia->GetNetCode();
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}
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WIRE_VIA* wire_via = &wire_vias[i];
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// example: (via Via_15:8_mil 149000 -71000 )
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PADSTACK* padstack = library.FindPADSTACK( wire_via->GetPadstackId() );
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if( !padstack )
|
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{
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|
// Dick Feb 29, 2008:
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// Freerouter has a bug where it will not round trip all vias. Vias which have
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// a (use_via) element will be round tripped. Vias which do not, don't come back
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// in in the session library, even though they may be actually used in the
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// pre-routed, protected wire_vias. So until that is fixed, create the padstack
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// from its name as a work around.
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wxString psid( FROM_UTF8( wire_via->GetPadstackId().c_str() ) );
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|
|
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THROW_IO_ERROR( wxString::Format( _( "A wire_via refers to missing padstack '%s'." ),
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|
psid ) );
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|
}
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|
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std::shared_ptr<NET_SETTINGS>& netSettings = aBoard->GetDesignSettings().m_NetSettings;
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|
|
|
int via_drill_default = netSettings->m_DefaultNetClass->GetViaDrill();
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|
|
|
for( unsigned v = 0; v < wire_via->vertexes.size(); ++v )
|
|
{
|
|
PCB_VIA* via = makeVIA( wire_via, padstack, wire_via->vertexes[v], netCode,
|
|
via_drill_default );
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|
aBoard->Add( via );
|
|
}
|
|
}
|
|
}
|
|
}
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|
|
|
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} // namespace DSN
|